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Scholar
Scholar
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Registered: ‎08-01-2012

[VHDL2019 Feature Request] Subtype of function Return Value infered from Context

I was previously instructed to request VHDL features one per post, so here we go. Im looking for the initial quality of life features of VHDL 2019 and I only care about support in synthesis.

Please add support for the ability of a function to infer it's subtype from the context of the function call.

eg.

function some_function(all_ones : boolean) return s of std_logic_vector is
  variable r : s'subtype;
begin
  r := (others => '1') when all_ones else (others => '0');
  return r;
end function.

..
signal s  : std_logic_vector(9000 downto 0);

..
s <= some_function(true);  -- function returns (9000 downto 0);
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