10-24-2016 06:27 AM
I'm a newbie in VHDL design. I have a doubt regarding different assignations to the same variable inside a process in a post-synthesized design.
For example the next code snippet:
--previous code p1 : process (clk,reset) variable a : std_logic; variable b : std_logic; begin a := '1' --some code here that modifies b variable if ( b = '1') then a := '0'; end if; end process;
--the code goes on
Can it be assured that during execution in FPGA, if b is '1', a always will be '0'. In other words, I know that during simulation all statements inside a process are executed sequentially, but can we say the same in relation to a synthesized design? Is the execution order inside the process sequential too?
10-24-2016 06:42 AM
Yes. It has to work that way to be at all useful. Otherwise variables would be for simulation only.
10-24-2016 08:14 AM
10-24-2016 08:26 AM
What I meant was that if Synthesis doesn't behave the same for variables as Simulation, then variables wouldn't be useful for synthesis.