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Highlighted
3,763 Views
Registered: ‎08-10-2016

Variable assignment inside a VHDL process in Synthesis

Hi all,

 

I'm a newbie in VHDL design. I have a doubt regarding different assignations to the same variable inside a process in a post-synthesized design.

 

For example the next code snippet:

 

--previous code

p1 : process (clk,reset)

  variable a : std_logic;
  variable b : std_logic;

begin
  a := '1'
  
 --some code here that modifies b variable

  if ( b = '1') then
    a := '0';
  end if;

end process;

--the code goes on

Can it be assured that during execution in FPGA, if b is '1', a always will be '0'. In other words, I know that during simulation all statements inside a process are executed sequentially, but can we say the same in relation to a synthesized design? Is the execution order inside the process sequential too?

 

Thanks!

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Professor
Professor
3,754 Views
Registered: ‎08-14-2007

Re: Variable assignment inside a VHDL process in Synthesis

Yes.  It has to work that way to be at all useful.  Otherwise variables would be for simulation only.

-- Gabor
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Highlighted
3,735 Views
Registered: ‎08-10-2016

Re: Variable assignment inside a VHDL process in Synthesis

Ok, thanks for the anwser.

But why should variables be for simulation only? I'm using variables in a combinational process. At the beginning I update them with the value of some signals and at the end I register them into the same signals. I'm using the two process methodology from Gaisler.
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Highlighted
Professor
Professor
3,731 Views
Registered: ‎08-14-2007

Re: Variable assignment inside a VHDL process in Synthesis

What I meant was that if Synthesis doesn't behave the same for variables as Simulation, then variables wouldn't be useful for synthesis.

-- Gabor
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