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Visitor
Visitor
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Registered: ‎06-25-2009

Verilog 2 dimentional memory assignment

 

When i use this type of implementation i can't assign any mem cell. All mem cell and also Dout are always stuck at "x". How can i make an assignment of mem bits. Thanks by now.

 

 

reg [0:10] mem[0:10];

 

always@(posedge clock)
        begin
            
                    mem[x] <= {Din , mem[x][0:9]};
                    Dout <= mem[x][x];
                        
                    
                    x <=x+1;

                    if(x==4'd10)
                        x<=4'd0;
                    
                    
        end 
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Historian
Historian
3,621 Views
Registered: ‎02-25-2008

Re: Verilog 2 dimentional memory assignment


yeaten wrote:

 

When i use this type of implementation i can't assign any mem cell. All mem cell and also Dout are always stuck at "x". How can i make an assignment of mem bits. Thanks by now.

 

 

reg [0:10] mem[0:10];

 

always@(posedge clock)
        begin
            
                    mem[x] <= {Din , mem[x][0:9]};
                    Dout <= mem[x][x];
                        
                    
                    x <=x+1;

                    if(x==4'd10)
                        x<=4'd0;
                    
                    
        end 

 
Your signal x is never initialized.
----------------------------Yes, I do this for a living.
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