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9,527 Views
Registered: ‎07-15-2015

Verilog Code for Division Operation which consumes minimum number of clock cycle?

Hello Everyone,

I am doing a project in which i have to design a module which does the division operation. I have designed a module for division but for n bit width data its taking n clock cycle for division. Please suggest some algorithm which take minimum number of clock cycle in order to perform a division operation.

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3 Replies
Teacher muzaffer
Teacher
9,495 Views
Registered: ‎03-31-2012

Re: Verilog Code for Division Operation which consumes minimum number of clock cycle?

No matter how you cut it, division is going to take a long time; either it's going to cost you cycles or it's going to cost you period ;-)

If you want to reduce number of cycles at the expense of a long period, you can take the logic in every cycle and attach it end to end. This will give you one cycle divide but you won't be happy with the timing results.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Scholar u4223374
Scholar
9,489 Views
Registered: ‎04-26-2015

Re: Verilog Code for Division Operation which consumes minimum number of clock cycle?

Just attaching it all end-to-end also tends to do horrible things to resource consumption.

 

What sort of numbers are you dividing? For small widths (eg. 8-bit divided by 4-bit) you can do the whole thing with a block RAM lookup table - so you can do two divisions per clock cycle. For larger values, there are fast division algorithms; these give much faster convergence but are also much more complex to implement (the single-bit-per-cycle method is very, very easy to implement).

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9,435 Views
Registered: ‎07-15-2015

Re: Verilog Code for Division Operation which consumes minimum number of clock cycle?

Sir, my data width is 16 bit

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