UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
1,772 Views
Registered: ‎11-22-2016

Verilog Coding Question - Initializing a register

Jump to solution

Hello All,

Let's say if I have a 

 

  output reg [267:0] tx_data;

 

How do I initialize the above tx_data to a zero or say a fixed value..

 

I know that we can initialize by using 268'h followed by hex values, but it would be a long line of code...Is there any other way to initialize the above register to a zero or a constant value?

 

Thanks,

Manoj

0 Kudos
1 Solution

Accepted Solutions
Scholar hbucher
Scholar
2,533 Views
Registered: ‎03-22-2016

Re: Verilog Coding Question - Initializing a register

Jump to solution

@manoj_xilinx

268'h0 will do it.

 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
0 Kudos
6 Replies
Scholar hbucher
Scholar
1,766 Views
Registered: ‎03-22-2016

Re: Verilog Coding Question - Initializing a register

Jump to solution

@manoj_xilinx 

You can do it in an initial block. It is synthesizeable in FPGAs (but not in general).

http://www.vitorian.com/x1/archives/572

But the right thing to do is to initialize it inside a reset block. Example:

 

always @ (posedge clock or posedge reset) begin
    if (reset) begin
        tx_data = .... 
    end else ...

    end
end

 

 

 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
Adventurer
Adventurer
1,758 Views
Registered: ‎11-22-2016

Re: Verilog Coding Question - Initializing a register

Jump to solution

Thanks for your reply @hbucher...so Do I still need to use 

tx_data = 268'h followed by 67 zeros?....

0 Kudos
Scholar hbucher
Scholar
2,534 Views
Registered: ‎03-22-2016

Re: Verilog Coding Question - Initializing a register

Jump to solution

@manoj_xilinx

268'h0 will do it.

 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
0 Kudos
Highlighted
Adventurer
Adventurer
1,747 Views
Registered: ‎11-22-2016

Re: Verilog Coding Question - Initializing a register

Jump to solution

Thank you @hbucher

Scholar dpaul24
Scholar
1,737 Views
Registered: ‎08-07-2014

Re: Verilog Coding Question - Initializing a register

Jump to solution

 

 

@hbucher,

INITIAL blocks are synthesizable, despite what they taught you at school. -- thats new to me!

btw - The vdo would have been better to view without that bkgnd music! :-)

http://www.vitorian.com/x1/archives/572

 

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
Scholar markcurry
Scholar
1,685 Views
Registered: ‎09-16-2009

Re: Verilog Coding Question - Initializing a register

Jump to solution

 

Just remember that using that definition of "initial" must be interpreted as "the value of that register after FPGA configuration".

 

This may or may not be what is desired / expected.

 

Regards,

 

Mark