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Visitor mahdiinaya
Visitor
1,158 Views
Registered: ‎03-19-2018

Verilog Options - Synthesis clog2

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I'm trying to use clog2 in my system verilog file.

Looking online, it looks like I need to update the verilog options to be 2005 or utilize the -sv directive. How is that possible since that window is grayed out.screenshot.PNG

Also, am I able to implement $clog(x), where x is dynamic? When doing that, I receive a synthesis error stating that x needs to be constant.

To get around the issue for now, I am using a macro..


`define CLOG2(x) \
((x <= 1) || (x > 512)) ? 0 : \
(x <= 2) ? 1 : \
(x <= 4) ? 2 : \
(x <= 8) ? 3 : \
(x <= 16) ? 4 : \
(x <= 32) ? 5 : \
(x <= 64) ? 6 : \
(x <= 128) ? 7: \
(x <= 256) ? 8: \
(x <= 512) ? 9 : 0

 

 

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Contributor
Contributor
1,104 Views
Registered: ‎10-25-2018

Re: Verilog Options - Synthesis clog2

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@mahdiinaya$clog2 is primarily used by the synthesis tool during the compilation phase to determine the size of data and address buses and what-not. For example:

parameter int MAX_ADDR = 10_000;
parameter int ADDR_WIDTH = $clog2(MAX_ADDR);

All SystemVerilog synthesis tools (should) support the $clog2 function in this manner, and Vivado does. It is at their discretion if they also allow it to be used to generate combinational logic similar to the macro you showed, but it would not be considered portable code. If you are interested in portability, then the macro is the way to go.

3 Replies
Historian
Historian
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Registered: ‎01-23-2009

Re: Verilog Options - Synthesis clog2

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So, first, in SystemVerilog, the system function is $clog2 (not $clog).

In "plain" Verilog, it was necessary to write a macro similar to the one you show.

I don't know about using Verilog 2005 - it may not be possible (or it may - I just don't know).

In SystemVerilog, you can use the $clog2 function.  So why not just use SystemVerilog. In almost all cases, SystemVerilog is backward compatible with Verilog (with the main exception being some more reserved keywords). So even if your code is "vanilla" Verilog, reading it as SystemVerilog will almost certainly work. This is done on the file by setting the FILE_TYPE property to SystemVerilog, or simply renaming the file to end with .sv (so the add_files will automatically recognize it as SystemVerilog.

Avrum

 

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Visitor mahdiinaya
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1,144 Views
Registered: ‎03-19-2018

Re: Verilog Options - Synthesis clog2

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I agree, $clog2 - sorry for the typo.

This is exactly what I have done. I don't use verilog files any more, rather systemverilog.

In simulation I could use the $clog2 function no problem. But in synthesis it returned:

[Synth 8-280] expression must be constant: argument to $clog2 

The macro I mentioned in the previous post synthesizes fine.

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Contributor
Contributor
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Registered: ‎10-25-2018

Re: Verilog Options - Synthesis clog2

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@mahdiinaya$clog2 is primarily used by the synthesis tool during the compilation phase to determine the size of data and address buses and what-not. For example:

parameter int MAX_ADDR = 10_000;
parameter int ADDR_WIDTH = $clog2(MAX_ADDR);

All SystemVerilog synthesis tools (should) support the $clog2 function in this manner, and Vivado does. It is at their discretion if they also allow it to be used to generate combinational logic similar to the macro you showed, but it would not be considered portable code. If you are interested in portability, then the macro is the way to go.