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Tom_Szymk
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Registered: ‎05-12-2021

Verilog configurations in Synthesis

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I am working on a project that has been using SV configurations and libraries as a mechanism to select which design versions are used in a particular simulation. Is there any way in which SV configurations can be used to determine which design source files are to be included for a particular synthesis/Implementation run in Vivado (in a similar way to how they are used for simulation)? 

I have looked around so far and I cannot find any information on use configurations in Vivado at all. I'd really appreciate it if you could clarify whether it is possible and if so, where I can find some more information on the matter.

Many thanks,

Tom

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Tom_Szymk
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Registered: ‎05-12-2021

After some more digging, I came across the following post, which confirms that the functionality I would like to use is not currently supported by Vivado synthesis: https://forums.xilinx.com/t5/Synthesis/SystemVerilog-Libraries-Why-aren-t-they-supported-by-Vivado/td-p/1128893

Additionally, I noticed the attached note within UG901 - Vivado Design Suite User Guide - Synthesis which also confirms that ther are not supported.

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UG901 - vivado configs.png
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Tom_Szymk
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Registered: ‎05-12-2021

After some more digging, I came across the following post, which confirms that the functionality I would like to use is not currently supported by Vivado synthesis: https://forums.xilinx.com/t5/Synthesis/SystemVerilog-Libraries-Why-aren-t-they-supported-by-Vivado/td-p/1128893

Additionally, I noticed the attached note within UG901 - Vivado Design Suite User Guide - Synthesis which also confirms that ther are not supported.

View solution in original post

UG901 - vivado configs.png