Verilog implicit nets

[kenryan2]

Is there a way to tell Vivado synthesis (2016.2) to refuse to accept an implicitly declared wire or reg?  I keep getting bit by a typo in a name happily synthesizing into a ground rather than getting flagged as an error.

Thanks

[tud_hartmann · Accepted solution]

Hi @kenryan2,

`default_nettype directive is what you are looking for. Simply write

`default_nettype none

at the beginning of your Verilog file, but don't forget to reset it at the end:

`default_nettype wire

Best Regards,

Stephan

[kenryan2]

Ah, thank you!