cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Scholar
Scholar
8,530 Views
Registered: ‎04-27-2010

Vivado 2015.4 BRAM utilisation

I have a Kintex 160T design that I run through synthesis. If I then look at the utilisation summary it says that it uses 128.5 BRAMs. If I then open the design and do a report_utilisation cmd it says that it uses 192 (36k) and 97 (18k). Why is the first figure lower than the actual?

0 Kudos
Reply
4 Replies
Scholar
Scholar
8,526 Views
Registered: ‎02-27-2008

bd,

 

Synthesis 'solves' the needs of the design by assigning the base tiles (elements) required.


Place then determines how to meet the needs, and modifies the design by actually choosing the physical blocks.  The numbers may (and do) change at this step.


Finally route connects the elements placed, and may rip up, replace, and reroute to finish the design, and meet timing.

 

Especially if resources are not all used (design is sparse) using more of anything is easier (and faster) and hence preferred (as time to a solution and bitstream is paramount).

 

Does that help?  Only the final design represents the usage:  everything prior is merely a reflection of what the tools at each step have done.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Reply
Scholar
Scholar
8,515 Views
Registered: ‎04-27-2010

Austin,

 

This is just the synthesis step before p&r. So if I open the synthesized design and run the report_utilisation cmd I get the numbers shown. But they are a lot different from the first number. The other values LUT, FF etc are correct.

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
8,514 Views
Registered: ‎09-20-2012

Hi @beandigital

 

Are you comparing the post synthesis utilization numbers generated by tool vs the ones seen with report_utilization command?

 

If OOC IP's in your design are contributing to the BRAM resources then the post synthesis report will not list these BRAM's as the IP will be considered as black box during synthesis. When you open synthesized design it loads IP DCP's hence it reports the total design utilization.

 

The post implementation utilization numbers generated by tool will include IP utilization too.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Reply
Xilinx Employee
Xilinx Employee
8,480 Views
Registered: ‎09-20-2012

Hi @beandigital

 

Did my earlier post answer your query? If no, please attach the snapshots of the reports which you are referring to.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Reply