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Vivado 2016.4 [Synth 8-27] wor declaration not supported

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Visitor
Posts: 1
Registered: ‎03-17-2017
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Vivado 2016.4 [Synth 8-27] wor declaration not supported

I'm trying to use a wired-or to tie together outputs from several different modules.  However this does not seem to be supported in Vivado 2016.4 Synthesis.  Is there a way to get this to work?  If not, is there a way to work around this?  I am just trying to tie a bus to all 0's as a default that the wired-or will override with any ones put on the bus by individual modules.


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Scholar
Posts: 937
Registered: ‎09-16-2009

Re: Vivado 2016.4 [Synth 8-27] wor declaration not supported

 

ISE supported this fine, and we used it extensively.  It is quite synthesizable - no issues at all.

 

We asked Xilinx to add this support BACK into Vivado.  They added the support BACK in to Vivado sometime in the 2015 timeframe, but default turned off.

 

To turn on this support, add the following to your synthesis build script.

 

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter compatibilityMode true"

 

I'm not sure why Xilinx hasn't turned this on by default.

 

Regards,

 

Mark

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Adventurer
Posts: 76
Registered: ‎11-22-2016

Re: Vivado 2016.4 [Synth 8-27] wor declaration not supported

I'm pretty sure that any form of wired signal resolution doesn't work with FPGA synthesis. You'll need to join your signals with an explicit OR somewhere.

After all, FPGAs don't implement the ability to drive any internal signal from more than one source at any one time.
Moderator
Posts: 5,297
Registered: ‎08-01-2008

Re: Vivado 2016.4 [Synth 8-27] wor declaration not supported

this is not supported . refer this ARs
https://www.xilinx.com/support/answers/65406.html
Thanks and Regards
Balkrishan
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Scholar
Posts: 937
Registered: ‎09-16-2009

Re: Vivado 2016.4 [Synth 8-27] wor declaration not supported

 

ISE supported this fine, and we used it extensively.  It is quite synthesizable - no issues at all.

 

We asked Xilinx to add this support BACK into Vivado.  They added the support BACK in to Vivado sometime in the 2015 timeframe, but default turned off.

 

To turn on this support, add the following to your synthesis build script.

 

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter compatibilityMode true"

 

I'm not sure why Xilinx hasn't turned this on by default.

 

Regards,

 

Mark