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Adventurer
Adventurer
1,236 Views
Registered: ‎03-28-2014

Vivado 2017.2 Synthesis bug

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I ran into a bug in Vivado 2017.2 where synthesis completes successfully despite a syntax error in my VHDL. The build doesn't fail until the opt_design step of implementation.

 

The code below is missing a closing parenthesis on the last 4 assignments. The file does get picked up as a "non-module" file, but it seems like this should produce at least a critical warning, if not an error, during synthesis.

 

process(slow_user_clk,slow_aresetn)
begin
	if slow_aresetn = '0' then
		usr_irq_req <= (others => '0');
		irq <= (others => '0');
	elsif rising_edge(slow_user_clk) then
		irq(0) <= irq_0_intr;
		irq(1) <= irq_1_intr;
		irq(2) <= irq_2_intr;
		irq(3) <= irq_3_intr;
		usr_irq_req(0) <= not usr_irq_ack(0) and (usr_irq_req(0) or (irq_0_intr and not irq(0)); -- Latch until cleared with usr_irq_ack
		usr_irq_req(1) <= not usr_irq_ack(1) and (usr_irq_req(1) or (irq_1_intr and not irq(1)); -- Latch until cleared with usr_irq_ack
		usr_irq_req(2) <= not usr_irq_ack(2) and (usr_irq_req(2) or (irq_2_intr and not irq(2)); -- Latch until cleared with usr_irq_ack
		usr_irq_req(3) <= not usr_irq_ack(3) and (usr_irq_req(3) or (irq_3_intr and not irq(3)); -- Latch until cleared with usr_irq_ack
	end if;
end process;
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Xilinx Employee
Xilinx Employee
1,962 Views
Registered: ‎02-16-2014

Re: Vivado 2017.2 Synthesis bug

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Hi @dcwhitehead

 

Filed CR#986169 for this.

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3 Replies
Xilinx Employee
Xilinx Employee
1,207 Views
Registered: ‎08-01-2008

Re: Vivado 2017.2 Synthesis bug

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yes it should produce critical warning . Check this related ARs
https://www.xilinx.com/support/answers/46901.html
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
1,193 Views
Registered: ‎03-28-2014

Re: Vivado 2017.2 Synthesis bug

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Did something change in the parser between 2017 and 2016? It seems like the 2016 and earlier versions of Vivado reported syntax errors earlier in the build.
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Xilinx Employee
Xilinx Employee
1,963 Views
Registered: ‎02-16-2014

Re: Vivado 2017.2 Synthesis bug

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Hi @dcwhitehead

 

Filed CR#986169 for this.

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