UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Xilinx Employee
Xilinx Employee
1,705 Views
Registered: ‎01-11-2011

Vivado 2018.1 Synthesis - [Synth 8-2947] errors when using VHDL-2008 in Windows

When using VHDL-2008 source files in Vivado 2018.1 on a Windows machine, users may get the following errors during Synthesis, or when using "Open Elaborated Design":

 

---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.273 ; gain = 111.703
---------------------------------------------------------------------------------
ERROR: [Synth 8-2947] error reading binary file 'C:/Xilinx/Vivado/2018.1/scripts/rt/data/vhdl/pkgs/2008/vdbs/ieee/std_logic_1164.vdb'
ERROR: [Synth 8-1086] ieee.std_logic_1164 failed to restore
ERROR: [Synth 8-4169] error in use clause: package 'std_logic_1164' not found in library 'ieee' [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:11]
ERROR: [Synth 8-2947] error reading binary file 'C:/Xilinx/Vivado/2018.1/scripts/rt/data/vhdl/pkgs/2008/vdbs/ieee/numeric_std.vdb'
ERROR: [Synth 8-1086] ieee.numeric_std failed to restore
ERROR: [Synth 8-4169] error in use clause: package 'numeric_std' not found in library 'ieee' [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:12]
ERROR: [Synth 8-2947] error reading binary file 'C:/Xilinx/Vivado/2018.1/scripts/rt/data/vhdl/pkgs/2008/vdbs/std/standard.vdb'
ERROR: [Synth 8-1086] std.standard failed to restore
ERROR: [Synth 8-4169] error in use clause: package 'standard' not found in library 'std' [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:13]
ERROR: [Synth 8-1031] string is not declared [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:14]
ERROR: [Synth 8-1031] std_ulogic is not declared [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:68]
ERROR: [Synth 8-1031] std_ulogic is not declared [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:69]
ERROR: [Synth 8-1031] std_ulogic is not declared [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:70]
ERROR: [Synth 8-2398] near string "PRIMITIVE" ; 0 visible types match here [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:74]
ERROR: [Synth 8-1031] std_ulogic is not declared [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:79]
ERROR: [Synth 8-1031] std_ulogic is not declared [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:80]
ERROR: [Synth 8-1031] std_ulogic is not declared [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:81]
ERROR: [Synth 8-2398] near string "PRIMITIVE" ; 0 visible types match here [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:85]
ERROR: [Synth 8-1031] bit is not declared [C:/Xilinx/Vivado/2018.1/scripts/rt/data/unisim_VCOMP.vhd:90]

This issue is not present for Linux users.

 

For Windows users, please use the below Answer Record and apply the patch to resolve this issue.

 

https://www.xilinx.com/support/answers/70908.html

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------