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Visitor leonnoordam
Visitor
465 Views
Registered: ‎11-09-2018

Vivado 2018.2 [Synth 8-27] actual generic type not supported

It has been three years since the topic here was started, but usage of VHDL-2008 generic types still results in the error message "[Synth 8-27] actual generic type not supported" in Vivado 2018.2.

What is the status of CR#844627? Are there any plans to implement this feature?

 

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8 Replies
Moderator
Moderator
382 Views
Registered: ‎07-21-2014

Re: Vivado 2018.2 [Synth 8-27] actual generic type not supported

@leonnoordam

This looks to be unsupported in 2018.2 as well. Can you please share your RTL file for us to understand the usage and to confirm whether this is supported or not?

Also, if this is not supported I will open a new CR to have this usage supported in next releases.

Thanks
Anusheel

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Visitor leonnoordam
Visitor
355 Views
Registered: ‎11-09-2018

Re: Vivado 2018.2 [Synth 8-27] actual generic type not supported

Thanks for your response.

As example code I have two VHDL files: my_register.vhd and my_top_level.vhd. The first is the actual use-case for generic types, the second is used to make the code synthesizable. The goal is to make the my_register entity independent of the input signal type. Normally, this entity would have std_logic_vector types as input and outputs, but these do not map automatically to record types. You would have to build a conversion function from std_logic_vector to my_record and vice versa. When using the my_register entity these conversion functions are not needed, reducing the effort to make a more generic component.

This code does not compile in Vivado 2018.2; both files were set to VHDL 2008.

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Observer stevecurrie
Observer
211 Views
Registered: ‎01-26-2016

Re: Vivado 2018.2 [Synth 8-27] actual generic type not supported

Bumping this in the hopes that this gets fixed. It's so frustrating to constantly be hamstrung by Vivado not supporting aspects of VHDL 2008. This one seems like it'd be widely useful, too!

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Moderator
Moderator
183 Views
Registered: ‎07-21-2014

Re: Vivado 2018.2 [Synth 8-27] actual generic type not supported

@leonnoordam

Your shared design is now passing in our internal builds without any error and you will be able to use this VHDL2008 feature in next releases.

@stevecurrie

This is already in the road-map and you will see better support in next releases.

Thanks
Anusheel 

Scholar richardhead
Scholar
169 Views
Registered: ‎08-01-2012

Re: Vivado 2018.2 [Synth 8-27] actual generic type not supported

@anusheel

Can you also confirm if all types will be possible? is this AR fixed?

https://www.xilinx.com/support/answers/66920.html

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Moderator
Moderator
162 Views
Registered: ‎07-21-2014

Re: Vivado 2018.2 [Synth 8-27] actual generic type not supported

@richardhead

I tested with std_logic_vector as datatype of record element, is there anything specific you would like me to check. I believe all the supported datatypes should be supported for this usage. 

Regarding the AR, the status is still the same and if any element of record is null then whole record will be treated as null. Please let me know if you see different results at your end.

Thanks
Anusheel 

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Scholar richardhead
Scholar
156 Views
Registered: ‎08-01-2012

Re: Vivado 2018.2 [Synth 8-27] actual generic type not supported

@anusheel

Do you have any reasons why 2008 features are being supported before VHDL 1993 bugs are fixed? This null record bug is really frustrating, to me, more so that not having other 2008 features. Vivado is the ONLY tool that has this bizarre issue.

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Moderator
Moderator
125 Views
Registered: ‎07-21-2014

Re: Vivado 2018.2 [Synth 8-27] actual generic type not supported

@richardhead

I see that there was one CR filed recently for below topic and this feature looks under development now:
https://forums.xilinx.com/t5/Synthesis/VHDL-Bug-Report-Vivado-Removes-non-null-port/td-p/847233

Thanks
Anusheel 

 

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