12-21-2018 08:41 AM
I'm building an 8-bit LFSR using this simple VHDL process:
tpgc: process (prbs0) is variable prbs0_v : std_logic_vector(7 downto 0); begin prbs0_v(0) := prbs0(1); prbs0_v(1) := prbs0(2) xor prbs0(0); prbs0_v(2) := prbs0(3); prbs0_v(3) := prbs0(4); prbs0_v(4) := prbs0(5) xor prbs0(0); prbs0_v(5) := prbs0(6) xor prbs0(0); prbs0_v(6) := prbs0(7); prbs0_v(7) := prbs0(0); -- assign to signal prbs0_nxt <= prbs0_v; end process tpgc;
When I use this code, the Synthesis (doesn't complete). If however, I use this slightly modified code, all is fine (but the code is ugly and only acceptable, as I use only 8 bits here; imagine a 32-bit LFSR coded that way...).
Note: I used this in a large project, so maybe it only hangs in there. But this change made the difference for the Synthesis to hang or not to hang.
tpgc: process (prbs0) is variable prbs0_v0 : std_logic; variable prbs0_v1 : std_logic; variable prbs0_v2 : std_logic; variable prbs0_v3 : std_logic; variable prbs0_v4 : std_logic; variable prbs0_v5 : std_logic; variable prbs0_v6 : std_logic; variable prbs0_v7 : std_logic; begin prbs0_v0 := prbs0(1); prbs0_v1 := prbs0(2) xor prbs0(0); prbs0_v2 := prbs0(3); prbs0_v3 := prbs0(4); prbs0_v4 := prbs0(5) xor prbs0(0); prbs0_v5 := prbs0(6) xor prbs0(0); prbs0_v6 := prbs0(7); prbs0_v7 := prbs0(0); -- concatenate and assign to signal prbs0_nxt <= prbs0_v7 & prbs0_v6 & prbs0_v5 & prbs0_v4 & prbs0_v3 & prbs0_v2 & prbs0_v1 & prbs0_v0; end process tpgc;
01-09-2019 08:54 AM
This issue is most likely not created directly by this code. I changed some other minor things in some other modules and now the synthesis hangs again, despite the changed code concerning this LFSR.
01-09-2019 09:38 PM
01-10-2019 02:19 AM
Actually I can't, because I have no idea what causes the hang. The design is huge and contains company IP that I can't share here.
It synthesized OK all the time. The last thing I did was changing a posedge FF to a negedge FF and some conditions of if clauses - nothing unusual and perfectly legal VHDL and SystemVerilog code. From just looking at the code, you won't see anything suspcious.
I had a similar problem with version 2017.4, but when I changed to 2018.2, the problem was gone. Next thing I would do is try out the latest version 2018.3, but here in the company network I can't download it, because it keeps failing to download some files.
01-10-2019 02:26 AM
Good to hear that 2018.2 works fine. There is a possibility that the issue that you are seeing in 2017.4 was reported to us and now fixed in latest releases. You can continue using 2018.2 as there are no hang issues.
01-10-2019 03:30 AM - edited 01-10-2019 03:31 AM
Sorry, you got me wrong. 2018.2 was fine with a different version of the code, when 2017.4 didn't work. Now, as I made further changes to my code, I have the problem again, but now with version 2018.2. That's why I wanted to try out 2018.3.
In the meantime I observed, that I get error reports, that indicate that the synthesis acutally doesn't hang but crash. Please find attached the log and dmp files (I had to zip it to get the dmp file uploaded).
Maybe there's at least some hint about the part of the design that causes the problem. Unfortunately the log file doesn't say much and the dmp file is a binary file, which I can't make any sense of.
01-15-2019 07:10 AM - edited 01-15-2019 07:11 AM
I tried with Vivado 2018.3 on two different computers.
* On one computer (Win 7 Home Premium, SP1, 64 bit) the synthesis spawns 1 additional process (can be observed in the Windows Task Manager) and completes successfully.
* On the other computer (Win 7 Enterprise SP1, 64 bit) the synthesis spawns 3 additional processes and hangs after ~10minutes. At this point in time it dumps the error log and dump files in the run directory (as attached in my previous post).
Both computers have quad-core Intel CPUs.
Maybe the problem would be solved, if I could limit the number of parallel processes, but I didn't find a setting for that anywhere.