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Registered: ‎08-02-2018

Vivado 2018.3/2019.1 Synthesis fails for VHDL configuration through for generate loop


I'm having trouble running synthesis on a design that includes a configuration of components that are instantiated inside a for…generate loop (see below for a small piece of code that reproduces the issue). Whenever a configuration references such components, I get the following critical warning:

 [Project 1-560] Could not resolve non-primitive black box cell 'inner' instantiated as 'inst/gen[0].inst'. 5 instances of this cell are unresolved black boxes. [/devel/teststuff/vivado_configuration_test/isolated/mwe.vhd:11]

If I try to continue with implementation anyway, the warning turns into this (unsurprising) error:

[DRC INBB-3] Black Box Instances: Cell 'inst/gen[0].inst' of type 'inner' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

Interestingly this only happens if the to-be-configured-component lives inside a for…generate block.
If the components live inside an if…generate block (or no generate block at all), everything works as expected.
So if this is supported/working for the if…generate case, I suspect it's also supposed to be supported/working for the for…generate case.
Is this actually the case and this is a synthesis bug, or is this the expected behaviour (or am I simply doing something wrong)?


Best regards,


Minimal reproducing example:

entity outer is -- This entity includes a component that will be configured
port(i: bit_vector(4 downto 0); o: out bit_vector(4 downto 0));
end entity;

architecture a of outer is
	component inner
		port(i: bit; o: out bit);
	end component;
	gen: for idx in 0 to 4 generate
		inst: inner port map(i => i(idx), o => o(idx));
	end generate;

-- If the for...generate were to be replaced with an if...generate
-- it synthesises without an issue:
-- gen: if true generate
-- inst: inner port map(i => i(0), o => o(0));
-- end generate; end architecture; entity to_be_configured is -- This will be used to configure 'outer' port(i: bit; o: out bit); end entity; architecture impl of to_be_configured is begin o <= not i; end architecture; configuration test_config of outer is for a for gen for all: inner use entity work.to_be_configured; end for; end for; end for; end configuration; entity testbench is port(i: bit_vector(4 downto 0); o: out bit_vector(4 downto 0)); end entity; architecture mwe of testbench is component outer port(i: bit_vector(4 downto 0); o: out bit_vector(4 downto 0)); end component; for inst: outer use configuration work.test_config; begin inst: outer port map(i => i, o => o); end architecture;

Schematic of the synthesised design of the testbench entity.




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3 Replies
Registered: ‎08-01-2012

Any particular reason for using configurations. They are now one of the least useful parts of VHDL. Now you can use direct instantiation it's just easier to use generates to pick which entity or architecture you want.

What are using using configurations for?

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Registered: ‎08-02-2018

In general I agree with you. In this instance however, I want to change the entity that is instantiated (as inner) in outer without changing the architecture of outer. Ever further, I want to have multiple instances of potentially different configurations (with the same architecture except for the used entity for inner) of outer in my design.
To my knowledge this can't really be done without configurations.

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