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horreinp
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Registered: ‎03-28-2008

Vivado 2019.1 inferring less BRAM and more DRAM

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On a project using Ultrascale device and 4x100G interfaces, we have been trying to migrate from Vivado 2018.2 to Vivado 2019.1. However, the design cannot be implemented in Vivado 2019.1.

After investigation, we see a lot of hold constraints violated at all steps (except routing) (WHS is -0.799ns, all paths are coming from ethernet interfaces). We also see that synthesis results are really different between the two tools: DRAM usage goes up (from 16326 to 32438), while BRAM goes down (1868.5 down to 870). This is causing issue as the design get crowded.

Is there any new option to use to get back to previous behavior (at least selectively)?

Pierre-Henri

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rshekhaw
Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @horreinp ,

One thing which can be tried out is to  back trace the DRAM in RTL module from which they are getting inferred and applying RAM_STYLE property as "block" on those in RTL code:

Check more about the attribute on page no.61:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

Thanks,

Raj

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rshekhaw
Xilinx Employee
Xilinx Employee
582 Views
Registered: ‎05-22-2018

Hi @horreinp ,

One thing which can be tried out is to  back trace the DRAM in RTL module from which they are getting inferred and applying RAM_STYLE property as "block" on those in RTL code:

Check more about the attribute on page no.61:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

Thanks,

Raj

View solution in original post

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