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Visitor
Visitor
268 Views
Registered: ‎04-22-2020

Vivado 2019.2 synthesis get stuck at one place

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Now the synthesis of this project will always stuck after a certain minutes, leaving a single process which occupies some CPU resource. Sometimes it even won't start, the CPU usage is % forever.

This problem is very annoying and I wasted so much time on it.

I tried many methods post on the forum. Including : Restart computer, moving project directories, create new object, set some synthesis parameters, change the number of process..... It seems like this kind of problems always happen, and the developers just randomly try again, even with your suggestions.

Environment: Windows10, Intel i5 6300 CPU, 8GB memory, 64bits.

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Visitor
Visitor
157 Views
Registered: ‎04-22-2020

Thanks for you addvices. Finally I found that it's because the RAM of my laptop is so small. I wish if some warnings can be prompted in next update. 

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Guide
Guide
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Registered: ‎01-23-2009

One  common cause of behavior like this is improper inference of RAMs.

In order to infer a RAM, the structure of the RTL code must match what the synthesis tool recognizes as a RAM - examples of this coding style are shown in both the manuals and the language templates in Vivado.

If you do not code using this structure, the tools may not be able to recognize the RAM, and, instead, infer flip-flops. A single RAMB36 instance would therefore be replaced with 36,000 flip-flops, and all the enable generation and MUXing around them to implement the function of the "not quite a RAM". The explosion in cell count and connectivity has been known to increase the work required to be done by synthesis by an immense amount, causing the memory footprint to expand (possibly causing swapping) and causing the CPU run times to increase dramatically. This is often seen as the tool "hanging", but it isn't really hung - people have reported it eventually completing days (like close to a week) later, with a massively over-utilized FPGA (using way more flip-flops than the device has due to the replacement of BRAMs by flip-flops).

So I would recommend you look at any code where you infer larger RAMs and make sure the coding style conforms to what synthesis is looking for (and to be sure that the code is actually coding for the behavior of the RAMB cells on the FPGA).

Avrum

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-05-2017

Hi @BenjiZhang 

UG901 contains a link where you can download example templates for inferring different types of RAM/ROMs. They are also available in the Vivado Tool itself under Language Templates.

If you can send the project to me I can take a look at it here also.

Best Regards.

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Visitor
Visitor
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Registered: ‎04-22-2020

Thanks for you addvices. Finally I found that it's because the RAM of my laptop is so small. I wish if some warnings can be prompted in next update. 

View solution in original post

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