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Adventurer
Adventurer
11,249 Views
Registered: ‎04-02-2010

Vivado: Instantiate verilog (non-standard library) from VHDL

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Tool: Vivado 2014.4

 

I'm interested in instantiating System Verilog files in VHDL.  My problem is that I have 2 files that implement different code but use the exact same naming.  The verilog modules are both called example_tb.  My thought is to compile them into distinct libraries and then use the library reference to distinguish between them when I instantiate them in VHDL.  So far my attempts have failed with the synthesis reporting "no such design unit 'example_tb'".

 

I have been able to successfully synthesize one of these files by compiling it into the standard xil_defaultlib library, but it seems that compiling it into another library won't work.

 

I appreciate any help you can give.

 

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Xilinx Employee
Xilinx Employee
19,688 Views
Registered: ‎10-24-2013

Re: Vivado: Instantiate verilog (non-standard library) from VHDL

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Hi,
This message was added to better match the verilog and system verilog spec which doesn't allow libraries such as the "xil_defaultlib" but simulation does. This can prevent possible confusion between synthesis and simulation and it the message was added to let users know this difference.
Thanks,Vijay
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Xilinx Employee
Xilinx Employee
11,235 Views
Registered: ‎04-16-2012

Re: Vivado: Instantiate verilog (non-standard library) from VHDL

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Hello,

Is the language set to VHDL in project settings?
Check the sources in the libraries tab of sources window and confirm that the files are associated to correct libraries?

Share the synthesis log file here.

Thanks,
Vinay
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Adventurer
Adventurer
11,225 Views
Registered: ‎04-02-2010

Re: Vivado: Instantiate verilog (non-standard library) from VHDL

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Attached are screen shots from the project plus the synthesis log file (fpga.vds).  I noticed the following lines in the log file which look like the source of the problem:

 

# read_verilog -library ddr4_lib -sv G:/Work/M454/tmp/MixedLanguageTest/mig_ddr4_0_example/mig_ddr4_0_example.srcs/sources_1/imports/mig_ddr4_0/tb/example_tb.sv


WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [G:/Work/M454/tmp/MixedLanguageTest/mig_ddr4_0_example/mig_ddr4_0_example.srcs/sources_1/imports/mig_ddr4_0/tb/example_tb.sv:]

 

Are there any clean work arounds for this issue or do I need to edit the IP generated SystemVerilig file so the module name is unique?

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Xilinx Employee
Xilinx Employee
19,689 Views
Registered: ‎10-24-2013

Re: Vivado: Instantiate verilog (non-standard library) from VHDL

Jump to solution
Hi,
This message was added to better match the verilog and system verilog spec which doesn't allow libraries such as the "xil_defaultlib" but simulation does. This can prevent possible confusion between synthesis and simulation and it the message was added to let users know this difference.
Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
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