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Visitor
Visitor
7,689 Views
Registered: ‎02-09-2011

Vivado [Synth 8-27] access type not supported

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Here is a simple function that converts bool to string.  It synthesizes fine in ISE 14.5, but chokes in Vivado 2013.1 (using Vivado synthesis defaults):

 

function sel(condition: boolean; a,b: string) return string is
variable x : line;
begin
  if condition then
    write(x,a);
  else
    write(x,b);
  end if;
  return x.all;
end function;

 

The synthesis error is on the return x.all line.  The error specifically is:

 

ERROR: [Synth 8-27] access type not supported.

 

My googling resulted in no hits on this error.  I am probably doing something foolish, but I sure can't figure it out.
  Any thoughts?

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Explorer
Explorer
10,293 Views
Registered: ‎04-09-2008

Understood.

 

The "access" keyword has special meaning in VHDL. It allows access to dynamically allocated data (like strings of undefined length). It works like a pointer in C. There isn't any real hardware meaning that I'm aware of.

 

I've never tried to synthesize these types in XST. My guess is that XST may have a built-in workaround to ignore those types and only throw warnings if related logic isn not pruned.

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Explorer
Explorer
7,684 Views
Registered: ‎04-09-2008
Is this VHDL? Is that write() function from the textio package?

The write() function is generally meant for debugging in a simulator. It is not synthesizable. You need to instruct your synthesis tool to ignore your sel function, or the parts in it that use the write() function.
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Visitor
Visitor
7,682 Views
Registered: ‎02-09-2011

I always forget the mundane details...

 

Yes it is VHDL.

 

Yes it uses the textio library, which is previously declared with the other libraries:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library std;
use std.textio.all;

 

Yes I agree it is not synthesizable.  It is used for conditional simulator behavior.

 

That said, the ISE 14.5 synthesizer does not choke on it.  Vivado 2013.1 does choke on it.  I am trying to determine what option I am missing in Vivado that seems to be turned on by default in ISE.  Or, perhaps the Vivado synthesis tool cannot ignore this construct.

 

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Explorer
Explorer
7,677 Views
Registered: ‎04-09-2008

Try wrapping the statements in

 

--synthesis translate_off

 

--synthesis translate_on

 

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Visitor
Visitor
7,653 Views
Registered: ‎02-09-2011

Thank you.

 

I was hoping to get more details on the Synth 8-27 error and exactly what syntax is inappropriate.

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Highlighted
Explorer
Explorer
10,294 Views
Registered: ‎04-09-2008

Understood.

 

The "access" keyword has special meaning in VHDL. It allows access to dynamically allocated data (like strings of undefined length). It works like a pointer in C. There isn't any real hardware meaning that I'm aware of.

 

I've never tried to synthesize these types in XST. My guess is that XST may have a built-in workaround to ignore those types and only throw warnings if related logic isn not pruned.

View solution in original post

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Highlighted
Explorer
Explorer
5,666 Views
Registered: ‎04-24-2014

You can solve your issue with the following code snippet. This can be used in simulation and synthesis.

 

    -- if-then-else function
    function ite(condition: boolean; a,b: string) return string is
    begin
      if condition then
        return a;
      else
        return b;
      end if;
    end function;

 

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