cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
8,999 Views
Registered: ‎10-01-2010

Vivado SystemVerilog synthesis does not recognize default argument values in `define macros

Jump to solution

Vivado synthesis (2015.2) does not recognize `define macros with default arguments, e.g. (registers.sv):

 

`define REGISTER_DATA(DIN, DOUT, CE = 1) \
   always_ff @(posedge clk_i) if (CE) DOUT <= DIN;

The synthesizer quits with:

 

ERROR: [Synth 8-2379] near = 1 : illegal macro parameter
[<work_dir>/registers.sv:23]

Questasim has no problem simulating this file. If I modify the design so it doesn't use defaults, synthesis completes successfully (registers_fixed.sv). See the SystemVerilog LRM (IEEE Std 1800-2012) section 22.5.1 for more information.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
17,025 Views
Registered: ‎07-21-2014

Re: Vivado SystemVerilog synthesis does not recognize default argument values in `define macros

Jump to solution

@tonyle

 

This feature is added in Vivado 2015.3, check attached schematic file.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
2 Replies
Highlighted
Moderator
Moderator
17,026 Views
Registered: ‎07-21-2014

Re: Vivado SystemVerilog synthesis does not recognize default argument values in `define macros

Jump to solution

@tonyle

 

This feature is added in Vivado 2015.3, check attached schematic file.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
Highlighted
Contributor
Contributor
8,913 Views
Registered: ‎10-01-2010

Re: Vivado SystemVerilog synthesis does not recognize default argument values in `define macros

Jump to solution

Kudos for getting this in so quickly.

0 Kudos