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Vivado active netlists limit

Posts: 1
Registered: ‎05-18-2017

Vivado active netlists limit

Hello everybody,

Whenever I try to Synthesize my design I get the following error:

[Common 17-70] Application Exception: Number of active netlists exceeds limit (255)

I looked everywhere I could, but I didn't find any information about what does this limit mean, and how to avoid this error.
Is this "active netlists limit" just a limitation of the software, or is it related to the capacity of the FPGA I'm using? Is there any way to avoid it, or do I have to redo my design in order to reduce the number of netlists?

Thanks in advance for the help,


Xilinx Employee
Posts: 895
Registered: ‎05-14-2008

Re: Vivado active netlists limit

Which Vivado version are you using?

Are you using a lot netlists (EDIF/NGC) in your design?

In which process did you receive this error? Looks like the error did not happen in Synthesis but at the beginning of Implementation, correct?

Can you post a screenshot of the Vivado GUI when this error occurs?