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xreves
Visitor
Visitor
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Registered: ‎05-10-2017

Vivado auto-derived or IP clocks not found when parsing XDC

Hello,

 

I have some problems constraining clocks and clock domains during synthesis.

 

1) Synthesis auto-derives clocks that are not found when parsing XDC file. As these clocks are not found with the tcl command "get_clocks" in XDC file, it is not possible to specify "set_clock_groups" or "set_false_path" constraints. 

 

However, these clocks are reported on the TCL Console when loading the synthesized design and also in the "Report Clock Interaction" tool. Even if the root clocks are constrained to set them asynchronous, this does not seem to be translated to the derived clocks. 

 

Then, how can these derived clocks be constrained if they are not found when parsing the XDC file? Notice that using the Tcl console I can successfully run the commands that fail in the XDC file once synthesis is completed.

 

2) On the other hand, with "report_compile_order -constraints" command I get a single constraints file for synthesis (my XDC file), while I get also the list of all IP XDC files for implementation, all properly sorted according to the EARLY, NORMAL or LATE attribute. However, in the synthesis report it looks like all files are parsed. But If I specify a clock in the XDC file that was created within one of the IP XCD files, it is again not found while parsing my XDC but it is found once synthesis has finished. Notice that clock is actually created in one IP XDC file processed before my XDC file.

 

For instance, in case of an auto-generated clock: 

Parsing XDC File [/local/Projects/Xilinx/test/test.srcs/constrs_1/new/design_constraints.xdc]
WARNING: [Vivado 12-627] No clocks matched 'sys_clk_clk_generator_0'. [/local/Projects/Xilinx/test/test.srcs/constrs_1/new/design_constraints.xdc:16]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/local/Projects/Xilinx/test/test.srcs/constrs_1/new/design_constraints.xdc:16]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks sys_clk_clk_generator_0]'. [/local/Projects/Xilinx/test/test.srcs/constrs_1/new/design_constraints.xdc:16]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.

And in case of a clock created within an IP XDC file:

WARNING: [Vivado 12-627] No clocks matched 'user_clk'. [/local/Projects/Xilinx/test/test.srcs/constrs_1/new/design_constraints.xdc:22]

While output of "report_clocks" after synthesis is:

...
Clock Period(ns) Waveform(ns) Attributes Sources gen_clk_p 10.000 {0.000 5.000} P {gen_clk_p} clkfbout_clk_generator_0 10.000 {0.000 5.000} P,G,A {CLK_MGR0/CLK_GEN/inst/plle2_adv_inst/CLKFBOUT} dly_clk_clk_generator_0 5.000 {0.000 2.500} P,G,A {CLK_MGR0/CLK_GEN/inst/plle2_adv_inst/CLKOUT0} sys_clk_clk_generator_0 10.000 {0.000 5.000} P,G,A {CLK_MGR0/CLK_GEN/inst/plle2_adv_inst/CLKOUT1} ddr_clk_p 10.000 {0.000 5.000} P {ddr_clk_p} user_clk 16.000 {0.000 8.000} P {regs0/control_interface_0/coms_interface/inst/aurora_8b10b_0_core_i/gt_wrapper_i/aurora_8b10b_0_multi_gt_i/gt0_aurora_8b10b_0_i/gtxe2_i/TXOUTCLK}
...

Then, the clocks exists and are created, but not "visible" when parsing my XDC file.

 

For me this is an unexpected behavior since I can't properly specify the timing constraints. Am I doing something incorrect? Any hint on what may be happening?

 

Thanks,

Xavier

 

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2 Replies
avrumw
Expert
Expert
2,093 Views
Registered: ‎01-23-2009

This is (at least partly) expected behavior.

 

XDC constraints are parsed twice - once at the beginning of synthesis and once again as synthesis is about to complete (or at the beginning of implementation, depending on whether you are using project or non-project mode).

 

During synthesis, any IP that is synthesized OOC is a black box for synthesis. As a result, any clock that is created inside the block does not yet exist.

 

However, once synthesis is completes, the OOC IP black boxes are "filled in" - this happens prior to the second reading of the XDC files. So, during this second reading, all constraints should be properly handled - including those that rely on the clocks generated in the IP.

 

You should be able to see this in the log files - you can see the two separate readings of the XDC and you will notice that the second reading doesn't give you any violations. So, your design is properly constrained for implementation (although it isn't for synthesis).

 

If this is acceptable to you (i.e. you are not synthesizing to the full set of constraints), then you can either ignore these critical warnings, or move the constraints that need the IP clocks to a separate constraint file and mark those as "USED_IN_IMPLEMENTATION" (only).

 

Another option would be to create another XDC file that contains "fake" clocks on the output clock ports of the IP, and mark this file USED_IN_SYNTHESIS (only). This way, these fake clocks would exist in synthesis (in place of the real ones inside the IP), and could be used for your constraints during synthesis. During implementation, this XDC file won't be read and the real clocks will come from the filled in representation of the IP (so you can have "full" constraints for both synthesis and implementation).

 

Avrum

xreves
Visitor
Visitor
2,042 Views
Registered: ‎05-10-2017

Hi Avrum,

 

Thanks for your guidance. 

 

I'll then write some "simple" constraints for synthesis (as user guide recommends) and the more detailed constraints left for implementation.

 

Thanks,

Xavier

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