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Observer nikhenri
Observer
460 Views
Registered: ‎05-15-2013

Vivado bug with back-to-back VHDL attribute, report false error "ERROR [Synth 8-5882] found unsupported attribute"

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Hi !

Is there a way to make make a back-to-back VHDL attribute work ?

The synthesis return a false error that the attribute is not supported, but the attribut is supported, it's seem having back-to-back attribute on Vivado cause an issue.

Exemple#1:

 

    signal clk_cnt      : integer range 100 downto 0 := 0;  
    signal clk_cnt2     : clk_cnt'subtype; --The attribute IS supported
...
    clk_cnt        <= clk_cnt + 1 when(clk_cnt /= clk_cnt'subtype'high); --expect '100' got [Synth 8-5882] found unsupported attribute
...

Exemple #2:

 

 

type t_array_slv        is array (natural range <>) of std_logic_vector;
signal adc_data_ch      : t_array_slv(1 downto 0)(2 downto 0);
signal adc_data_ch2 : adc_data_ch'element; --the attribute IS supported
... adc_data_ch <= std_logic_vector(to_unsigned(adc_data, adc_data_ch'element'length)); --expect '3' got [Synth 8-5882] ... ...

It work well on Modelsim.

I tested and see the issue on the following version : 2016.4 & 2017.3

 

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1 Solution

Accepted Solutions
Moderator
Moderator
353 Views
Registered: ‎03-16-2017

Re: Vivado bug with back-to-back VHDL attribute, report false error "ERROR [Synth 8-5882] found unsupported attribute"

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Hi @nikhenri ,

 

I have created small testcase and checked with latest internal build and it still throws the same error for back to back VHDL attribute. Hence, the CR has been filed on it. Let developers look into it may make necessary changes in upcoming Vivado versions.  

Regards,
hemangd

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5 Replies
Moderator
Moderator
392 Views
Registered: ‎07-21-2014

Re: Vivado bug with back-to-back VHDL attribute, report false error "ERROR [Synth 8-5882] found unsupported attribute"

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@nikhenri

I doubt this is supported in Vivado, let me check and get back.

Thanks
Anusheel 

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Scholar richardhead
Scholar
376 Views
Registered: ‎08-01-2012

Re: Vivado bug with back-to-back VHDL attribute, report false error "ERROR [Synth 8-5882] found unsupported attribute"

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'subtype has been confirmed as supported by xilinx

https://forums.xilinx.com/t5/Synthesis/VHDL-2008-Enhancement-request-subtype-attribute/m-p/839896

 

And given that 'element works, then chained attributes must work or there is a VHDL compile bug.

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Moderator
Moderator
354 Views
Registered: ‎03-16-2017

Re: Vivado bug with back-to-back VHDL attribute, report false error "ERROR [Synth 8-5882] found unsupported attribute"

Jump to solution

Hi @nikhenri ,

 

I have created small testcase and checked with latest internal build and it still throws the same error for back to back VHDL attribute. Hence, the CR has been filed on it. Let developers look into it may make necessary changes in upcoming Vivado versions.  

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Observer nikhenri
Observer
314 Views
Registered: ‎05-15-2013

Re: Vivado bug with back-to-back VHDL attribute, report false error "ERROR [Synth 8-5882] found unsupported attribute"

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Thank you

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Moderator
Moderator
299 Views
Registered: ‎03-16-2017

Re: Vivado bug with back-to-back VHDL attribute, report false error "ERROR [Synth 8-5882] found unsupported attribute"

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Hi @nikhenri ,

 

Since the CR has been filed on this issue, please close the thread by marking it as accepted solution.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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