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Visitor
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Registered: ‎10-29-2008

Vivado can not detect FSM

Hi! I have spent a lot of time to get vivado to detect one of my FSMs. I have read the vivado coding guide, and can not understand why it is not detected. I have found which part of the code I must change to get it detected, but I can not figure out why. Is it my code, or a bug in Vivado?

I have attached a capture of the part of the code

If I switch the states in internalCtrl.vhd line 450 and 453, the FSM is detected, but of course, the code is not functional

I have also attached the vivado project.

Cheers Daniel!

 

fsm.jpg

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Scholar
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Registered: ‎08-07-2014

Re: Vivado can not detect FSM

@danielreidal,

and can not understand why it is not detected.

Please explain what it means by "not detected".

Can you not not pass RTL compilation? Have you simulated your design and can you see the FSM states changes? Or do you mean Vivado synthesis engine does not infer state-machines?

I also don't see the default when others => state.

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Voyager
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Registered: ‎06-20-2012

Re: Vivado can not detect FSM

@danielreidal 

Your design has several very critical warnings.

WARNING: [Synth 8-3848] Net incXReg in module/entity internalCtrl does not have driver. [H:/XILINX/TestFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/internalCtrl.vhd:71]

Correct them before continuing.

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Re: Vivado can not detect FSM

Sorry for my late response, have been out of office and ill for a couple of days.

When reading you reply I understand that I missed some important information. The subject should be "FSM is not inferred". The design is tested in hardware and fully functional, and this code is a part of a larger design that I can not post on official forums. As I can see in the xilinx coding guide, they do not use "when others" (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf). I usually use that statement, but I removed it to get my code as similar to the guide as possible. 

The reason why I found this issue was that my code sometimes failed during hardware testing. I found out that I forgot to remove one unused state in my signal that defines all states. So when I removed this extra state, all seems fine. But the issue with no inferred FSM remains. And it is a little bit scary that my FSM was not functional with this extra unused state, I mean, there was actually no code written to enter this state?

 


*** Running vivado
with args -log internalCtrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source internalCtrl.tcl


****** Vivado v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

Sourcing tcl script 'C:/Users/dr/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
source internalCtrl.tcl -notrace
WARNING: [Board 49-91] Board repository path '{C:UsersdrGoogle' does not exist, it will not be used to search board files.
WARNING: [Board 49-91] Board repository path 'DriveJobbDigitaltasys3 ivado-boards-master
ewoard_files}' does not exist, it will not be used to search board files.
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 14936
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 845.203 ; gain = 233.863
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'internalCtrl' [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/internalCtrl.vhd:59]
INFO: [Synth 8-638] synthesizing module 'spiSlaveHeader' [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/spiSlaveHeader.vhd:54]
INFO: [Synth 8-638] synthesizing module 'edge_detect' [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/edge_detect.vhd:17]
INFO: [Synth 8-256] done synthesizing module 'edge_detect' (1#1) [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/edge_detect.vhd:17]
INFO: [Synth 8-256] done synthesizing module 'spiSlaveHeader' (2#1) [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/spiSlaveHeader.vhd:54]
INFO: [Synth 8-638] synthesizing module 'spiSlave' [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/spiSlave.vhd:52]
INFO: [Synth 8-256] done synthesizing module 'spiSlave' (3#1) [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/spiSlave.vhd:52]
INFO: [Synth 8-638] synthesizing module 'spiSlave__parameterized0' [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/spiSlave.vhd:52]
INFO: [Synth 8-256] done synthesizing module 'spiSlave__parameterized0' (3#1) [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/spiSlave.vhd:52]
INFO: [Synth 8-638] synthesizing module 'blk_mem64x16' [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.runs/synth_1/.Xil/Vivado-13616-DRPC/realtime/blk_mem64x16_stub.vhdl:21]
INFO: [Synth 8-638] synthesizing module 'Prescaler' [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/Prescaler.vhd:46]
INFO: [Synth 8-256] done synthesizing module 'Prescaler' (4#1) [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/Prescaler.vhd:46]
INFO: [Synth 8-638] synthesizing module 'spiMasterDelay' [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/spiMasterDelay.vhd:46]
INFO: [Synth 8-256] done synthesizing module 'spiMasterDelay' (5#1) [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/spiMasterDelay.vhd:46]
INFO: [Synth 8-256] done synthesizing module 'internalCtrl' (6#1) [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/sources_1/new/internalCtrl.vhd:59]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 920.762 ; gain = 309.422
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 920.762 ; gain = 309.422
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 920.762 ; gain = 309.422
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.031 . Memory (MB): peak = 920.762 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.srcs/constrs_1/new/io.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/internalCtrl_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/internalCtrl_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1016.262 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1016.262 ; gain = 0.000
Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1016.262 ; gain = 404.922
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1016.262 ; gain = 404.922
Applied set_property DONT_TOUCH = true for memory_inst. (constraint file auto generated constraint, line ).
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1016.262 ; gain = 404.922
INFO: [Synth 8-802] inferred FSM for state register 'spiState_reg' in module 'spiSlaveHeader'
INFO: [Synth 8-802] inferred FSM for state register 'spiState_reg' in module 'spiSlave'
INFO: [Synth 8-802] inferred FSM for state register 'spiState_reg' in module 'spiSlave__parameterized0'
INFO: [Synth 8-802] inferred FSM for state register 'memState_reg' in module 'internalCtrl'
INFO: [Synth 8-3354] encoded FSM with state register 'spiState_reg' using encoding 'sequential' in module 'spiSlaveHeader'
INFO: [Synth 8-3354] encoded FSM with state register 'spiState_reg' using encoding 'sequential' in module 'spiSlave'
INFO: [Synth 8-3354] encoded FSM with state register 'spiState_reg' using encoding 'sequential' in module 'spiSlave__parameterized0'
INFO: [Synth 8-3354] encoded FSM with state register 'memState_reg' using encoding 'one-hot' in module 'internalCtrl'
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1016.262 ; gain = 404.922
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\memSpi_inst/spiTransmitReg_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\RegSpi_inst/spiTransmitReg_reg[0] )
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[1]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[2]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[3]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[4]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[5]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[6]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[7]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[8]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[9]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[10]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[11]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[12]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[13]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[14]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[15]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[16]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[17]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[18]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[19]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[20]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[21]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[22]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[23]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[24]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[25]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[26]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[27]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[28]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[29]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3886] merging instance 'spiMast_inst/spiStateNext_reg[2]' (FDRE) to 'spiMast_inst/spiStateNext_reg[1]'
INFO: [Synth 8-3886] merging instance 'ErrorRegister_reg[30]' (FDRE) to 'ErrorRegister_reg[31]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\ErrorRegister_reg[31] )
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1016.262 ; gain = 404.922
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1016.262 ; gain = 404.922
Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1016.262 ; gain = 404.922
Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1026.402 ; gain = 415.063
Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1032.051 ; gain = 420.711
Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1032.051 ; gain = 420.711
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1032.051 ; gain = 420.711
Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1032.051 ; gain = 420.711
Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1032.051 ; gain = 420.711
Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1032.051 ; gain = 420.711

Report Cell Usage:
+------+-------------+------+
| |Cell |Count |
+------+-------------+------+
|1 |blk_mem64x16 | 1|
|2 |BUFG | 1|
|3 |CARRY4 | 18|
|4 |LUT1 | 36|
|5 |LUT2 | 19|
|6 |LUT3 | 132|
|7 |LUT4 | 30|
|8 |LUT5 | 67|
|9 |LUT6 | 87|
|10 |FDRE | 689|
|11 |FDSE | 44|
|12 |IBUF | 8|
|13 |OBUF | 10|
+------+-------------+------+
Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1032.051 ; gain = 420.711
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1032.051 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1033.227 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1033.227 ; gain = 694.707
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1033.227 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/testFSM/HYMS_CTRL_FPGA_testFSM/3547_HYMS_CTRL_FPGA.runs/synth_1/internalCtrl.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file internalCtrl_utilization_synth.rpt -pb internalCtrl_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed May 20 08:55:13 2020...

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Voyager
Voyager
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Registered: ‎06-20-2012

Re: Vivado can not detect FSM

" And it is a little bit scary that my FSM was not functional with this extra unused state, I mean, there was actually no code written to enter this state?"

It is just a guess.

If the original FSM had 9 states, it was encoded with 4 bits and 7 possible states in hardware were not described.

With 8 states this does not happen.

In any case it is a design problem.

ErrorRegister_reg is always zero. It'is not an error but strange.

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Visitor
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Registered: ‎10-29-2008

Re: Vivado can not detect FSM

Yes maybe, but strange behaviour anyhow. The errorregister is a remaining from the full design, nothing to worry about.

The question remains why the FSM is not inferred? And why it is inferred by just switching to states?

Cheers Daniel

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Voyager
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Registered: ‎06-20-2012

Re: Vivado can not detect FSM

Share the code the previous one had many warnings.

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Registered: ‎10-29-2008

Re: Vivado can not detect FSM

Here is the project.

Cheers Daniel

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Vivado can not detect FSM

 am just reading through this thread - and while I cannot diagnose the problem, I thought I would bring some things up.

Usually, when a state machine has more than a handful of states (>3  and  < 64 I think)  Vivado will encode the state as a one hot bit vector. So each state has its own bit, and in theory no two bits should ever be high at the same time. This makes it easy for state detection (you can just check the state of one bit).

In VHDL, I would recommend you do not use a "when others =>" for a state machine and a case statement for two reasons

1. If you add more states, they will be covered by this others state by default, and if you forget a state, it will do whatever is in the when others.

2. Without a when others, it is a simple syntax error if you forget to explicitly cover a state. So it wont compile if there is a state that is not covered. (If Vivado does allow this to compile, it is a Vivado bug).

FSM detection using enumerated types is something that has been around a long time, so I would always be sceptical about a tool bug. Any error during runtime I would always suspect to be a design bug. Your code is pretty standard synchronous state machine code.

What kind of testbenching did you do on the design? Do you have good coverage (both function and code) during the tests? Code coverage is part of any paid for simulator, and can be a quick check that states are not covered during testing - so if you have any states missed, try and get them covered during testing - you may find your bug.

 

NOTE: None of your signals except the state machine are reset in your SM code. You have actually connected the rst to the clk enable pin of all the regisers. This seems to be a common issue in all of your code. You have three options to fix this:

1. Reset everything

2. Separate rese and non-reset registers into separate processes (with the current if/else style)

3. Put the reset as a separate if at the bottom of the process;

See this for an explanation:

https://stackoverflow.com/questions/61794336/are-multiple-non-nested-if-statements-inside-a-vhdl-process-a-bad-practice

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Registered: ‎10-29-2008

Re: Vivado can not detect FSM

Hi I have not used any code coverage at all. I mean, its a very simple state machine and I can see that no states are missed. Or am I missing something?  I have also verified the FSM with chipscope.

I now see the problems with my reset of the FSM. My mistake, and I will correct the code. Thanks for your inputs.

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Vivado can not detect FSM

More than likely, its getting locked in a state because the inputs are not what you expected.

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