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Visitor bodox
Visitor
147 Views
Registered: ‎01-31-2019

Vivado exported VHDL netlist port problem

Dear all,

Exported VHDL netlist swaps direction of ports vs RTL source - leading to a (simulation) bug

?

Thank you,

Bodo

 

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2 Replies
Xilinx Employee
Xilinx Employee
140 Views
Registered: ‎05-14-2008

Re: Vivado exported VHDL netlist port problem

Can you provide more details?

Which Vivado version are you using?

What command were you using to export the VHDL netlist, write_vhdl?

What is the port like in your original code and what is it like in the exported netlist file?

What's more, one thing you can do now for investigation is to check the direction of the port in the post-synth netlist (open synthesized design and check the schematic of the port).

-vivian

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Visitor bodox
Visitor
51 Views
Registered: ‎01-31-2019

Re: Vivado exported VHDL netlist port problem

>Can you provide more details?

>Which Vivado version are you using?

2018.2

>What command were you using to export the VHDL netlist, write_vhdl?

The problem shows during simulation with Cadence Incisive, not with Mentor Questasim. And it is going wrong during the elaboration.

>What is the port like in your original code and what is it like in the exported netlist file?

Module from Xilinx in the schematic: axi_emc, port MEM_CEN is not in the schematic as it is the start-up interface of the Xilinx module.

Module in VHDL: axi_emc_v3_0_17, from Xilinx, line 284 for port mem_cen, (0 to 1), for component “axi_emc”, with “C_USE_STARTUP = 1” and “C_NUM_BANKS_MEM = 1”.

Module in VHDL: axi_emc_v3_0_vh_rfs.vhd, line 3646 for port mem_cen, ((C_NUM_BANKS_MEM-1) downto C_USE_STARTUP), so leading to (0 to 1) connected to (0 downto 1), as both constants have been defined above.

 

>What's more, one thing you can do now for investigation is to check the direction of the port in the post-synth netlist (open synthesized design and check the schematic of the port).

The schemaqtic after synthesis does not contain the MEM_CEN bus.

 

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