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Voyager
Voyager
4,959 Views
Registered: ‎10-06-2015

Vivado not reporting correct 'error'

This problem had me running in circles for a while.  Granted, I have a source code issue that I'm working through.  During simulation I am asserting  signals, call them COEF_RD_LEAD and COEF_RD_TRAL.  When looking at it in simulation the signal was X.  I searched down to the source and saw that it was driven but when it makes it to the top level it's an X.  So I dug through the source code and noticed my error; I had assigned to two different signals to the same top level PORTS.  That's my error.

 

..
..
COEF_RD_LEAD            <= int_coef_rd;
COEF_RD_TRAL            <= int_coef_rd;
..
..
COEF_RD_LEAD            <= int_coef_rd_lead;   
COEF_RD_TRAL            <= int_coef_rd_tral;    
..
..

Then I decided to find out why Vivado didn't warn me.  I do have hundreds of warnings (that's another complaint about IPs dishing out lots of needless warnings that I've been told to ignore), and thought that's perhaps how I missed this one.  So I did a edit-find in files command looking for COEF_RD_LEAD and this is what was reported:

WARNING: [Synth 8-3848] Net int_coef_rd_tral in module/entity READ_SIDE_ENGINE does not have driver. [C:/xproj_nov/AIB_SRC/AIB_SRC.srcs/sources_1/imports/new/READ_SIDE_ENGINE.vhd:172]

This seems in error, shouldn't Vivado report that the PORT has two drivers?

 

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9 Replies
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Xilinx Employee
Xilinx Employee
4,933 Views
Registered: ‎04-16-2012

Re: Vivado not reporting correct 'error'

Hi @steve_av

 

Can you share the testcase?

 

Thanks,

Vinay

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Voyager
Voyager
4,914 Views
Registered: ‎10-06-2015

Re: Vivado not reporting correct 'error'

I archived the project after I found this so I do have a zip file of the entire project.  It's a 33MB file so I'm not sure I can attach a file that large.  If you message me with an easy move invitation I can send it to you that way.

 

 

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Xilinx Employee
Xilinx Employee
4,907 Views
Registered: ‎04-16-2012

Re: Vivado not reporting correct 'error'

Hi @steve_av

 

I will send you ezmove link soon.

Please upload your project.

 

Thanks,

Vinay

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Moderator
Moderator
4,904 Views
Registered: ‎07-01-2015

Re: Vivado not reporting correct 'error'

Hi @steve_av,

 

Is this issue seen in Vivado 2016.3 or any other version?

Thanks,
Arpan
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Voyager
Voyager
4,900 Views
Registered: ‎10-06-2015

Re: Vivado not reporting correct 'error'

Just sent the file via ezmove...

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Voyager
Voyager
4,899 Views
Registered: ‎10-06-2015

Re: Vivado not reporting correct 'error'

this is with 2016.2, I have 2016.3 but haven't migrated the project to 2016.3 yet so I can't say for certain this problem is seen in 2016.3

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Xilinx Employee
Xilinx Employee
4,872 Views
Registered: ‎05-07-2015

Re: Vivado not reporting correct 'error'

HI @steve_av

Are you doing a post synth/ post impl simulation? 
The error you showed is  about "int_coef_rd_tral" net  not having a driver and is clearlt not related to  "COEF_RD_TRAL" being driven by two drivers.
 My hunch is that  "int_coef_rd_tral" is trimmed out because it does not have a driver and hence COEF_RD_TRAL does report to have multiple drivers



Thanks
Bharath
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Voyager
Voyager
4,867 Views
Registered: ‎10-06-2015

Re: Vivado not reporting correct 'error'

just behavioral simulation.  I do have (had) a bug in my code where I had two signals tied to the same port.  One signal was actually driven by some logic (which was correct) but the other signal I had inadvertently tied to the same PORT was just a dangling signal.  That signal was defined but never tied off to logic (didn't have a driver).  So I had one signal that did have a driver and another signal that did NOT have a driver tied to the same PORT.  The tool reported back the PORT didn't have a driver when it probably should have reported back that two signals were tied to the port.

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Xilinx Employee
Xilinx Employee
4,842 Views
Registered: ‎05-07-2015

Re: Vivado not reporting correct 'error'

HI @steve_av

 

Tool will report a warning for  "Multi Driven nets". as the word it self says, it is only relevant if the signal is "driven"  by separate  signals. In this case,  as one of the connected nets is  not driving the  PORT as that net itself does not have any driver and would have  been eliminated  during synthesis anyway there will be no Multi driven nets warnings during synthesis.

Hence if you would have done post synthesis simulation , COEF_RD_TRAL  port would not  have shown X  as  the driverless net  "int_coef_rd_tral" connected to it would have  removed during synthesis.

Note: If you are curious, you can assign driver to the "int_coef_rd_tral" signal  and you will  surely see a warning  on COEF_RD_TRAL about  being a multi driven net, during synthesis.

Thanks
Bharath
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