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Explorer
Explorer
12,821 Views
Registered: ‎09-16-2010

Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated.

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Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated. 

 

See attached.

 

If I explicitly tell it to use block ram with ram_style set as "block" I get the warning:

 

"WARNING: [Synth 8-3463] Infeasible ramstyle = block set for RAM RAM_A_reg,trying to implement using LUTRAM"

 

The fix, as shown in the attached file, is to put the two ram read statements in different processes. 

 

Note that this issue is not seen with other synthesis tools. 

Andrew
1 Solution

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Xilinx Employee
Xilinx Employee
19,327 Views
Registered: ‎11-28-2007

Re: Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated.

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Hi Boots,

 

I understand your frustration, however officially we only supported what was shown in the XST templates.


I will start an internal discussion and see what are official statement is and if we plan to make any enhancements.

 

 

Best regards

Dries

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Xilinx Employee
Xilinx Employee
12,804 Views
Registered: ‎11-28-2007

Re: Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated.

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Hi Andrew,

 

unfortunately, we only support and test for the memory templates that are supplied with Vivado (see the templates window)

We don't have a concatenated memory template.

 

However, I think it is possible to do what you want to do.

Basically, you need to cut the memories and put them into separate modules.

In the wrapper of these 2 memories, you can concatenate the outputs.

 

Side-note: you don't use the output pipeline register. The performance of your memories could be a limiting factor in the performance of your design.

 

 

Best regards,

Dries

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Explorer
Explorer
12,737 Views
Registered: ‎09-16-2010

Re: Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated.

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I was hoping this would generate a change request. Shouldn't Vivado synthesis support the same RAM inferrence as other tools, including ISE? Shouldn't the RAM inferrence be made more robust? 

 

I would like to point out that RAM inferrence issues cause a big headache when migrating to Vivado. It forces the Xilinx 7 series customer to go over every block ram in the design to ensure that Vivado has implemented it correctly and if not, to modify what could be library code. Code which is likely already in use in existing products and will have to be retested. This generates a level of uncertainty.  

 

 

Andrew
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Xilinx Employee
Xilinx Employee
19,328 Views
Registered: ‎11-28-2007

Re: Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated.

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Hi Boots,

 

I understand your frustration, however officially we only supported what was shown in the XST templates.


I will start an internal discussion and see what are official statement is and if we plan to make any enhancements.

 

 

Best regards

Dries

--------------------------------------------------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
12,708 Views
Registered: ‎11-28-2007

Re: Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated.

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Hi Boots,

 

I got a positive response and approval to file a CR.

No commitment on when it will be fixed, but in general we do indeed claim compatibility with XST, so thank you for reporting this!

Also thanks for supplying a testcase! This helped to reproduce the issue and made it easier to file the CR.

 

 

Many thanks!

Dries

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Explorer
Explorer
12,706 Views
Registered: ‎09-16-2010

Re: Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated.

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No problem. Thanks for the feedback! :)

Andrew
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Highlighted
10,002 Views
Registered: ‎10-12-2009

Re: Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated.

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Hi Dries,

I want to inform you about onotherone problem with BLOCK RAM implementation.

Vivado synthesis cannot infer block RAM when Single-Port Block RAM is defined inside GENERATE block like in next example. ISE handle it correctly.

 

type t_hil_lut_mem is array (0 to (2 ** (HIL_LUT_ADDR_WIDTH+1))-1) of std_logic_vector(HIL_DATA_WIDTH-1 downto 0);
type t_hil_lut_mem_array is array (0 to HIL_LUT_NO_OF_UNITS-1) of t_hil_lut_mem;

signal lut_mem                 : t_hil_lut_mem_array := LUT_INIT_ARRAY;  

.

.

.

GEN_LUTS: for i in 0 to NO_OF_LUTS-1 generate 

  LUT_MEM_PROC : process (i_clk) begin
  if (rising_edge(i_clk)) then
    if (cb_mem_we(i) = '1') then
      lut_mem(i)(to_integer(unsigned(cb_addr(i)))) <= i_cb_wr_data(DATA_WIDTH-1 downto 0);
    end if;
  lut_mem_data(i) <= lut_mem(i)(to_integer(unsigned(lut_addr))); -- int read
  end if;
  end process;

  cb_addr(i) <= unsigned(not(field_select(i)) & cb_mem_addr);
end generate;

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Explorer
Explorer
3,332 Views
Registered: ‎01-02-2012

Re: Vivado synthesis cannot infer block RAM when two dual-port RAM read data are concatenated.

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Three years have passed... Such funny limitations still exist :(

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