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juanfrias
Visitor
Visitor
858 Views
Registered: ‎11-06-2018

Viviado generates incorrect logic

I have this code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity Driver is
    generic(    max_num : integer := 19);
    Port (  clk, clk_fpga, input : in std_logic;
            EN : out std_logic;
            data_sipo : in std_logic_vector(10 downto 0);
            ps2_code : out std_logic_vector(7 downto 0));
end Driver;

architecture Behavioral of Driver is
signal start_temp, EN_temp, ps2_code_new : std_logic:= '0';
signal counter : integer range 0 to max_num := 0;
signal in_temp0, in_temp1 : std_logic; -- signals for edge detection
signal ps2_code_temp : std_logic_vector(7 downto 0);

begin
process(clk)
begin
    if falling_edge(clk) then
        if input = '0' and start_temp = '0' then
            start_temp <= '1';
        end if;
        if counter = max_num then
            start_temp <= '0';
        end if;
    end if;
    
    if rising_edge(clk) then
            if counter = max_num then
                start_temp <= '0';
            end if;
        end if;
    
end process;

process(clk)
begin
        if falling_edge(clk) then
            if start_temp = '1' then
                if counter = max_num then
                    EN_temp <= '1';
                    counter <= 0;
                else
                counter <= counter + 1;
                EN_temp <= '0';
                end if;
            end if;
        end if;
        
        if rising_edge(clk) then
                    if start_temp = '1' then
                        if counter = max_num then
                            EN_temp <= '1';
                            counter <= 0;
                        else
                        counter <= counter + 1;
                        EN_temp <= '0';
                        end if;
                    end if;
                end if;
end process;

process(clk_fpga)
begin 
    if rising_edge(clk_fpga) then
        if ps2_code_new <= '1' then
            ps2_code <= data_sipo(8 downto 1);
        end if;
    end if;
end process;

edge_detector : process(clk_fpga)
begin
if rising_edge(clk_fpga) then
    in_temp0 <= EN_temp;
    in_temp1 <= in_temp0;
end if;
end process;
ps2_code_new <= not in_temp1 and in_temp0;
EN <= ps2_code_new;

end Behavioral;

First. As you can see EN <= ps2_code_new, and ps2_code_new is a condition to identify where is a rising_edge on the signal EN_temp and EN_temp changes value from other conditions. So, if see the RTL schematic you'll notice this:

EN_disconnected.PNG

EN is grounded and ps2_code_new is disconnected and I don't understand why. I don't recieve any warning from Vivado that explain this.

 

Second. This is the piece of code that drives ps2_code:

process(clk_fpga)
begin 
    if rising_edge(clk_fpga) then
        if ps2_code_new <= '1' then
            ps2_code <= data_sipo(8 downto 1);
        end if;
    end if;
end process;

But if you see the RTL schematic ps2_code is only driven by a Flip Flop, and if I'm not wrong that isn't the code that I wrote to drive ps2_code(I cannot see the conditions about ps2_code_new, that is unconnected).

ps2_code.PNG

I would apreciate your help.

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2 Replies
dm78
Adventurer
Adventurer
848 Views
Registered: ‎03-15-2012

Maybe Vivado generates incorrect logic because you describes impossible logic (ok, Vivado should throw an error, but anyway)? You are using rising_edge and falling_edge on the same signals, which is not possible (at least in FPGAs). Every Flipflop has ONE clock input which can be locally inverted (for falling_edge), but does not have 2 clock inputs nor one input sensitive to both edges.

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drjohnsmith
Teacher
Teacher
840 Views
Registered: ‎07-09-2009

why do you want to use both edges of the clock ?
In the old days, and in GaN logic, it used to be used as the D flops had a positive hold time requirement, but any fpgas your going to use now, don't have that restriction ,

If you do want to code with both edges,
then one register has to be on one edge, and a separate one on the other edge. use two separate processes to code that.
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