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ciaran_toner
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Registered: ‎05-10-2017

Warning assignment ignored

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Hi, I wish to infer a DSP for a multiplication however the I get the warnings:

 

"WARNING: [Synth 8-3919] null assignment ignored [C:/... :25]"

"WARNING:[Synth 8-3919] null assignment ignored [C:/... :25]"

"WARNING:[Synth 8-3919] null assignment ignored [C:/... :26]"

"WARNING:[Synth 8-3919] null assignment ignored [C:/... :26]"

"WARNING:[Synth 8-3919] null assignment ignored [C:/... :49]"

"WARNING:[Synth 8-3919] null assignment ignored [C:/... :49]"

"WARNING:[Synth 8-3919] null assignment ignored [C:/... :49]"

 

 

I was wondering what is the cause of these warnings. Can I safely ignore them or is there a reason I am getting them?

 

I have attached the VHDL file I use for the multiplier below.

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balkris
Xilinx Employee
Xilinx Employee
5,092 Views
Registered: ‎08-01-2008
You can ignore this warning as not critical . It is a highly generic core. Null ranges are valid VHDL. As part of the warning reduction EoU initiatlve I've requested that they be included as part of the downgrade attribute so they will no longer be generated as warnings but is info. But I believe that this should be the default behaviour of Vivado synthesis as, already stated, this is a valid VHDL usecase and Questa does not feel the need to generate the warnings. As long as there are no range mismatches in assignments then there is no problem.
Thanks and Regards
Balkrishan
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florentw
Moderator
Moderator
3,139 Views
Registered: ‎11-09-2015

Hi @ciaran_toner,

 

Are these warning pointing to the VHDL file you sent? Did you connected the reset to the block?

 

You need to give a bit more information if you want explanation?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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balkris
Xilinx Employee
Xilinx Employee
5,093 Views
Registered: ‎08-01-2008
You can ignore this warning as not critical . It is a highly generic core. Null ranges are valid VHDL. As part of the warning reduction EoU initiatlve I've requested that they be included as part of the downgrade attribute so they will no longer be generated as warnings but is info. But I believe that this should be the default behaviour of Vivado synthesis as, already stated, this is a valid VHDL usecase and Questa does not feel the need to generate the warnings. As long as there are no range mismatches in assignments then there is no problem.
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

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