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Visitor
Visitor
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Registered: ‎12-24-2018

Why does synthesis add leaf cells from other modules into modules?

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Hello, I had a sort of question of why vivado is doing what it does in synthesis.

I have attached images of the RTL analysis and synthesized blocks of  the same cell, and noticed that vivado is bringing a bunch of leaf cells from another block into this block. why is this? It is kind of causing me headaches when I am trying to do changes of constraints based on cells. Is this a feature, and is there some way I can maintain the heirarchy of blocks I have?

Synthesis.PNG
RTL.PNG
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

This is due to the cross hierarchy boundaries optimization when flatten_hierarchy option set to rebuilt (default value).

You can add "keep_hierarchy = 'yes' " attribute to the module in RTL to prevent this.

-vivian

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Xilinx Employee
Xilinx Employee
300 Views
Registered: ‎05-14-2008

This is due to the cross hierarchy boundaries optimization when flatten_hierarchy option set to rebuilt (default value).

You can add "keep_hierarchy = 'yes' " attribute to the module in RTL to prevent this.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Teacher
Teacher
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Registered: ‎07-09-2009
Its called optimisation,

Your code describes the logic function you want, and your timing constrains define how fast you need it to go,

The synthesiser, is like a C compiler in that it does not take your code and implement it as is, its trying to speed it up / fit it better into the chip.

One of the things it does is moves registers around,
register push back / duplication to make parallel paths.

All very normal and expected.

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