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Visitor danm992
Visitor
448 Views
Registered: ‎10-03-2018

Why is vivado acting like I have two 'default' statements?

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The error is only showing up for line 484, and I don't understand why it's treating that case statement as if it has multiple default cases when I have only specified one. I have tried switching to non-blocking statements, I've tried using "assign", but I don't understand what is making this still happen. Help?!

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Historian
Historian
399 Views
Registered: ‎01-23-2009

Re: Why is vivado acting like I have two 'default' statements?

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So the actual error (as @xilinxacct mentioned) is the fact that each case item can have only one "statement". If you want more than one statement per case item, each case item must be enclosed in a begin/end.

Since case 8'h03: has no begin/end, the only statement in it is the assignment to rlu000 - therefore the assignment to LPC_reg is "something else" - the synthesizer is (at least initially) treating it as a statement that is always executed...

But you have other problems as well:

  • LIR_reg, LFR and LPC_reg are defined in the scope of your always block - therefore they will not be accessible outside that block. While this isn't necessarily an error (it may be depending on what else you need to do with these variables), it is "unusual coding style" and should be avoided
  • You are using blocking assignments in your always @(posedge clk) statement - I don't know if these things are just temporary variables or are supposed to represent flip-flops - if the latter, then they need to use non-blocking assignments

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Teacher xilinxacct
Teacher
419 Views
Registered: ‎10-23-2018

Re: Why is vivado acting like I have two 'default' statements?

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@danm992

I am not an expert on SystemVerilog, but I think you need a 'begin ... end' .. when you have multiple statements in a case.

Hope that helps

If so, please mark as solution accepted. Kudos also welcomed. :-)

Historian
Historian
400 Views
Registered: ‎01-23-2009

Re: Why is vivado acting like I have two 'default' statements?

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So the actual error (as @xilinxacct mentioned) is the fact that each case item can have only one "statement". If you want more than one statement per case item, each case item must be enclosed in a begin/end.

Since case 8'h03: has no begin/end, the only statement in it is the assignment to rlu000 - therefore the assignment to LPC_reg is "something else" - the synthesizer is (at least initially) treating it as a statement that is always executed...

But you have other problems as well:

  • LIR_reg, LFR and LPC_reg are defined in the scope of your always block - therefore they will not be accessible outside that block. While this isn't necessarily an error (it may be depending on what else you need to do with these variables), it is "unusual coding style" and should be avoided
  • You are using blocking assignments in your always @(posedge clk) statement - I don't know if these things are just temporary variables or are supposed to represent flip-flops - if the latter, then they need to use non-blocking assignments

Avrum

Visitor danm992
Visitor
362 Views
Registered: ‎10-03-2018

Re: Why is vivado acting like I have two 'default' statements?

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Thank you both! I knew that begin and end tags were used in certain circumstances, but I didn't realize it was to help it realize that there was a multi-level statement. I never realized that each case in a case-switch statement was by default only allowed to be one line. 

 

Thanks again!

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