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Registered: ‎02-20-2010

Why the clock period is 10 times the timing delay?

   I met a trobule when i tried the xilinx application note xapp460:video connectivity using TMDS I/O in spartan-3a FPGAs.
   The synthesis timing detail is below, why the total delay is 2.684ns but the "Clock period" is 26.844ns ?



Timing Detail:
All values displayed in nanoseconds (ns)

Timing constraint: Default period analysis for Clock 'RX_TMDS<3>'
  Clock period: 26.844ns (frequency: 37.252MHz)
  Total number of paths / destination ports: 33186 / 2492
Delay:               2.684ns (Levels of Logic = 1)
  Source:            hdmi_tx0/serialise/fdc_ra0 (FF)
  Destination:       hdmi_tx0/serialise/fd_db0 (FF)
  Source Clock:      RX_TMDS<3> rising 5.0X
  Destination Clock: RX_TMDS<3> rising 5.0X +180

  Data Path: hdmi_tx0/serialise/fdc_ra0 to hdmi_tx0/serialise/fd_db0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            34   0.495   1.073  hdmi_tx0/serialise/fdc_ra0

     RAM16X1D:DPRA0->DPO   1   0.562   0.357 


     FDE:D                     0.197          hdmi_tx0/serialise/fd_db0
    Total                      2.684ns (1.254ns logic, 1.430ns route)
                                       (46.7% logic, 53.3% route)




   The HDMI video frequency needs 74.25MHz, but this timing constraint makes the max frequency to 37.252MHz.
   Please tell me why and how to solve it.
   The attachments is the design files of xapp460  .

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