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Participant
Participant
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Registered: ‎07-23-2010

XST different estimations for same circuit

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Hello everybody,

 

I would like to post my problem since it is making me crazy. First of all, I designed a circuit in ISE, and when I synthetize it with XST I obtain the following estimations:

 

smooth6.png

 

To design it, I used some VHDL components that at last they were totally useless, so I deleted them from the project, and after synthetizing again I get the same estimations.

 

But I have created a new project and I have added a copy of the VHDL components used in the previous circuit, and, after synthetizing, instead of giving the same estimations than before, it  gives:

 

crazy.png

 

As you can see, the comsumption of FPGA space is much higher, being the same circuit with the same configuration...

 

Please any idea about why this is happening???

 

Thanks in advance!

Alejandro Cristo
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Participant
Participant
6,063 Views
Registered: ‎07-23-2010

Ok,

 

I found the error. I cleaned the original first project and synthetized it again, and the estimation is like the second one (the case with most space in the FPGA)... :(  I think it was taking some old useless files from who knows where...

 

By the way, is there any way to see the space required for each VHDL component (for each component of the hierarchy), not only for the top level?? It would be really useful to know what component are needed to optimize...

 

Thanks!

Alejandro Cristo

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Advisor
Advisor
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Registered: ‎10-05-2010

If the components really were 'totally useless', then the synthesiser might have deduced that they could be trimmed from the design completely. You would need to read through the reports to see exactly what has happened. Perhaps there were subtle differences or typos?

 

Different but similar designs may pack into slices differently, but only severe trimming would cause a reduction in DSP48Es from 117 to 13.

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Participant
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Registered: ‎07-23-2010

But it is quite strange. In the first project I have a top level called 'smooth', and the useless VHDL components were totally removed from the project... The second project is exactly the same, with the same files (copy of them), and the estimations are so different...

 

Any idea please?

Alejandro Cristo
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Participant
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Registered: ‎07-23-2010

Ok,

 

I found the error. I cleaned the original first project and synthetized it again, and the estimation is like the second one (the case with most space in the FPGA)... :(  I think it was taking some old useless files from who knows where...

 

By the way, is there any way to see the space required for each VHDL component (for each component of the hierarchy), not only for the top level?? It would be really useful to know what component are needed to optimize...

 

Thanks!

Alejandro Cristo

View solution in original post

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Explorer
Explorer
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Registered: ‎10-05-2010

@alejandrocristo wrote:

 

By the way, is there any way to see the space required for each VHDL component (for each component of the hierarchy), not only for the top level?? It would be really useful to know what component are needed to optimize...

 

 

 

PlanAhead shows the resources for each hierarchical block.

 

---

Joe

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