06-01-2021 10:31 PM - edited 06-01-2021 10:32 PM
I have an SV file which I try to compile using xvlog:
But the above command is throwing errors like "ERROR: [VRFC 10-2939] 'logic' is an unknown type".
Seems like the tool (Vivado 2018.3) is considering xyz.sv as verilog file while invoking xvlog. But the file type under the file properties of xyz.sv is already set correctly as 'System Verilog'. The file compiles and simulates successfully in GUI. But xvlog command on TCL console fails. What am I missing?