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Contributor
Contributor
1,621 Views
Registered: ‎10-16-2017

Xilinx roadmap for VHDL support

Is there any roadmap available for Xilinx customers, that would present when certain VHDL features will be implemented?

 

It is 2019 and soon we will have VHDL-2019, but Vivado support for VHDL-2008 is still rather poor.

I can provide some examples that would make VHDL code less verbose and that do not look like extremely hard to implement:

1. [Synth 8-26] formal function conversion in port map not implemented.

User can't write 

       my_conversion_function(q_o)       => my_signal

Instead one needs to define extra signal and convert in extra line with concurrent assignment or convert multiple times on input port mapping of other entities instantiation.

2. No support for VHDL contexts.

 

Maybe Xilinx should open source some parts of its tools, so that users can contribute and add features by themself?

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13 Replies
Scholar dpaul24
Scholar
1,607 Views
Registered: ‎08-07-2014

Re: Xilinx roadmap for VHDL support

@mkru,

Keep fighting, arguing.....

Many members have been doing this since the launch of Vivado.

I guess Xilinx is focussing more on data center applications, AI applications, etc..............which brings them revenue!

Since Vivado/ISE is free they care less about it.

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Scholar richardhead
Scholar
1,583 Views
Registered: ‎08-01-2012

Re: Xilinx roadmap for VHDL support

Unfortunately, VHDL support does not sell chips.

You'd probably get all the support you want if you had a few $10s of million to slap down on a massive chip order over the next few years, but as you likely dont, you'll have to join the queue with the rest. 

The problem is current support is "good enough" for both VHDL and Verilog. The big push is to HLS because the number of engineers that can write C is far greater than those that write HDL, and the great thing about HLS is you get a big innefficient deisgn that needs a big fat expensive FPGA, hopefully on a Xilinx dev board.

Then factor in all the big server market they're pushing for. All the dev work will likely be done in Verilog. 

Vivado will also always lag behind on sim support because again, its currently "good enough". Anyone with any proper simulation/verification requirement probably has the money to shell out on an ActiveHDL or Modelsim licence (You could even go an get modelsim for free from Intel!)

Moderator
Moderator
1,558 Views
Registered: ‎03-16-2017

Re: Xilinx roadmap for VHDL support

Hi @mkru ,

Regarding - [Synth 8-26] formal function conversion in port map not implemented 

my_conversion_function(q_o)       => my_signal

This feature of VHDL-2008 has already been reported and in roadmap for development. I have checked it internally. CR is already filed and PR is going to be filed on it. 

If you do not have further queries on it then close this thread by marking it as accepted solution. 

 

Regarding VHDL contexts : 

Create a new thread for this query. We will answer it in new thread. One thread should contain one query only. 

Also provide a testcase of VHDL contexts with that new thread so i can raise a discussion with the development on it. 

Regards,
hemangd

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Scholar dpaul24
Scholar
1,555 Views
Registered: ‎08-07-2014

Re: Xilinx roadmap for VHDL support

@hemangd,

This feature of VHDL-2008 has already been reported and in roadmap for development. I have checked it internally. CR is already filed and PR is going to be filed on it.

An honest and frank question arising in my mind due to the above statement.

For every VHDL2008 feature (not implemented till Vivado 2018.3) do we need to file a thread in this forum (and supported by other memebers here) so that it gets CR-ed and PR-ed for future Vivado roadmap?

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All PMs will be ignored
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Contributor
Contributor
1,534 Views
Registered: ‎10-16-2017

Re: Xilinx roadmap for VHDL support

@hemangd 

What about making some parts of your tools open source? Especially these related with VHDL or Verilog support.

You are really lagging behind with them and there are a lot Xilinx customers (maybe not the big ones, but a lot of small ones) so frustrated that they are ready to implement the standards features for you for free.

It seems to be win-win scenario, doesn't it?

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Contributor
Contributor
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Registered: ‎10-16-2017

Re: Xilinx roadmap for VHDL support

@richardhead 

I also start thinking that there are more marketing ** in the HLS than the truth. Do you have any reference for what you write that HLS can produce inefficient designs?

Recently I have read this: https://www.xilinx.com/products/design-tools/vivado/verification-and-debug.html
They claim that ,,10 frames of video data simulated ~12000x faster in C than HDL.,, This number 12000 seems to be really high. Of course they do not provide you with any source codes so that you could check it yourself.

Teacher drjohnsmith
Teacher
1,499 Views
Registered: ‎07-09-2009

Re: Xilinx roadmap for VHDL support

Been working with a team that has HLS people.
Yes HLS can be as good as hand coded,
Yes HLS can produce code faster than hand coded,

But, HLS is great at algorithms, terrible at timing,

C will always simulate faster than HDL, C only has two states 1 and 0, HDL has 9.

Processor are aimed at running C code, not HDL code,

The examples for HLS tend to be algorithmic, and floating point, thus highlighting how good it is.

As for does the C code make as good code as Hand coded HDL ?

May be, may be not.

Its the old question from the dawn of time over compilers .

I worked with some engineers once, who were Experts in a processor, they knew all the opp codes off by heart, they could even multiply hex numbers in their head,

They wrote the most amazing code for the application, fitted into the most amazingly small space, but a year later they had left.

Luckily it was not me, but there was the damdest to modify that code.

The second machine, we put ina bigger memory, and coded in C , the new language at the time, code was 100 times bigger , slower, but did the job, and was maintainable.

Now ask the same question, is C or assembly better ?


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Moderator
Moderator
1,483 Views
Registered: ‎03-16-2017

Re: Xilinx roadmap for VHDL support

Hi @dpaul24 ,

>>For every VHDL2008 feature (not implemented till Vivado 2018.3) do we need to file a thread in this forum (and supported by other memebers here) so that it gets CR-ed and PR-ed for future Vivado roadmap?

If you are facing issues due to this, then please post your query in new thread we will try to help you out. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Moderator
Moderator
1,480 Views
Registered: ‎03-16-2017

Re: Xilinx roadmap for VHDL support

Hi @mkru ,

>>What about making some parts of your tools open source? Especially these related with VHDL or Verilog support.

You can discuss with your Local FAE/sales representative or Xilinx FAE about non technical queries. 

 

As i mentioned earlier, the one VHDL-2008 feature which you mentioned is already in process and will be released with next Vivado versions. 

About VHDL contexts, please create a new thread for this another query with a testcase. 

If you do not have further technical queries please close this thread by marking it as accepted solution. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Teacher drjohnsmith
Teacher
1,465 Views
Registered: ‎07-09-2009

Re: Xilinx roadmap for VHDL support

As the thread title is "Xilinx roadmap for VHDL support "

and we don't have a road map for that, it woudl seem strange to call this questoin answered or closable.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Moderator
Moderator
1,424 Views
Registered: ‎10-04-2011

Re: Xilinx roadmap for VHDL support

Hello @mkru ,

I wanted to address the issue of C simulation performance improvement relative to RTL. I think that value is not as far off as you might expect. The issue with RTL verification is that it is a cycle-accurate simulation of all logic gates in the design. Further, within that clock cycle, many delta cycles compute the intermediate values of the logic before the final registered value for each bit of the design logic.  For a video frame, which contains many millions of individual pixels being operated on, with many color bits per pixel, this can result in an enormous amount of calculations for each clock cycle of the RTL design. In addition, the RTL design will contain many logic functions outside the video processing algorithm itself such as clocking, asynchronous FIFOs, and I/O alignment. All these functions themselves take many 1000’s of CPU clock cycles to compute the next value of each RTL cycle. Because of this, the clear advantage is to the C compiler which operates at the algorithm level, ignoring the gate level behavior of the final components. While marketing will seek to highlight the best case scenario, and not all algorithms will obtain the high level of performance improvement of video designs,  I don’t think the result for Video processing is that far off.

OK, thank you Michal, and let me know if you have any questions,

Scott

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Teacher hgleamon1
Teacher
1,377 Views
Registered: ‎11-14-2011

Re: Xilinx roadmap for VHDL support


C will always simulate faster than HDL, C only has two states 1 and 0, HDL has 9.


Well, that's only true if you are using resolved logic. It's possible to write VHDL without using std_logic (ulogic, bit, etc.).

I have no idea how Verilog handles logic resolution.

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Scholar richardhead
Scholar
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Registered: ‎08-01-2012

Re: Xilinx roadmap for VHDL support

"C will always simulate faster than HDL, C only has two states 1 and 0, HDL has 9. "

It is even more complicated than that. std_logic/ulogc have 9 states (4 states in verilog for the usual reg type) but you also need to consider signal/variable. Signals also have to store scheduling for each signal because you need to store the current state, and the state it will become in N deltas time. For more logic, this should only be current and next delta, but consider something like this:

a <= '1', '0' after 10 ns, 'H' after 20 ns, '-' after 100 ns;

Thats 9 possible states stored for each update needed, and then 4 times that state will change. Now also worry about stuff like inertial, transport, force and complexity just explodes.

Verilog has various phases which make it even more complicated I think, but overall is fairly similar.

HDL was designed to simulate logical circuits. C is a software language to create sequential programs.

Comparing the two isnt really fair.