06-10-2021 08:11 AM
Why do I encounter this problem?Or can I ignore this message?
`timescale 1ns / 1ps
parameter ROM_WIDTH = 36;
parameter ROM_ADDR_BITS = 9;//2^n can cover the amount of this stage
(* ROM_STYLE="BLOCK" *) //(* ROM_STYLE="DISTRIBUTED" *) or (* ROM_STYLE="AUTO" *)
reg [ROM_WIDTH-1:0] rom_0_0_0 [511:0];
reg [ROM_WIDTH-1:0] out;
wire [ROM_ADDR_BITS-1:0] addr;
wire [1:0] command;
$readmemb("Data/Module0/StageR1_0", rom_0_0_0, 0, 511);//0~ n-1 for the amount
always @(posedge clk_match)
out <= rom_0_0_0[addr];
out <= 0;
06-10-2021 11:06 PM
I am quite not sure which version of vivado you are using.
the message you mentioned is it a warning or error or critical warning ???
I tried the above mentioned code and its tools was inferring Block ram.
Make sure the mem file correctly. missing mem file may lead to the issue
06-10-2021 11:13 PM - edited 06-10-2021 11:36 PM
Thank you for your reply.
The tool I use is ISE 14. 7.
The above message is just a warning.
And I also confirmed that the mem file is in the file path. So I want to ask if this warning can be ignored?
06-11-2021 12:25 AM
I am using the same version of ISE. The only difference between your code and my code is, I have given the complete path path to my the mem file.
Can you try the following.
1. If you are using a xst project try copying the mem file to the location where the the design file(i.e both the design file and mem file should be in same directory) is and just give the mem filename like
$readmemb("<memfile_name>", rom_0_0_0, 0, 511);//0~ n-1 for the amount.
2. is this is not possible try giving the absolute path in $readmemb command.
Let me know if that helps