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4,501 Views
Registered: ‎01-19-2009

Xst block ram extraction failure

Hi,

 

when the block ram byte write enable port is connected to certain types of internal logic, Xst incorrectly implements the memory on LUTs when targeting (at least) Spartan-6. The source code below can be used to reproduce the problem on 14.7.

 

Sebastien

 

module memtest(
input clk,
input [9:0] adr,
input [31:0] dat_w,
output [31:0] dat_r,
input [3:0] wex
);

 

wire [3:0] we;
reg [31:0] mem[0:1023];
reg [9:0] memadr_r;


always @(posedge clk) begin
if (we[0])
mem[adr][7:0] <= dat_w[7:0];
if (we[1])
mem[adr][15:8] <= dat_w[15:8];
if (we[2])
mem[adr][23:16] <= dat_w[23:16];
if (we[3])
mem[adr][31:24] <= dat_w[31:24];
memadr_r <= adr;
end

 

assign dat_r = mem[memadr_r];

 

reg toggle;
always @(posedge clk) toggle <= ~toggle;

 

// This causes the RAM to be implemented on LUTs
assign we = toggle ? 15 : 0;

 

// With this instead, the BRAM is correctly used
//assign we = wex;

 

endmodule

 

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4 Replies
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Teacher
Teacher
4,492 Views
Registered: ‎03-31-2012

Re: Xst block ram extraction failure

Try registering we signal and see if that helps.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Highlighted
4,485 Views
Registered: ‎01-19-2009

Re: Xst block ram extraction failure

Even if it helps, Xst still does the wrong thing for the original code and should be fixed.
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Teacher
Teacher
4,483 Views
Registered: ‎03-31-2012

Re: Xst block ram extraction failure

Depends on how you define "wrong". XST is a synthesis tool. In Verilog there are no requirements on how memory should be synthesized. XST tries to extract block ram from your code and usually works if your code complies with a relatively strict template. As long as XST manages to generate code which behaves like the RTL its output is "right"; whether it should do what you want it to is open to discussion.
If you really want block ram when XST doesn't infer it, you have two options: 1) add synthesis constraints in your code to direct it. This may or may not work either but it usually gives better results than inference. 2) Instantiate block ram directly: this almost always (;-) works.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Guide
Guide
4,477 Views
Registered: ‎01-23-2009

Re: Xst block ram extraction failure

XST is particularly picky with the coding style required for byte enabled block RAMs. You should use the template provided in the language template in ISE - click on the little "lightbulb" in the menu bar.  Then expand

 

Verilog -> Synthesis Constructs -> Coding Examples ->RAM -> BlockRAM ->Single Port -> Byte-wide Write Enable

 

And select the most appropriate RAM from that list for the Spartan-6 (and newer) devices.

 

The comment at the top of one of these says

 

// Important!
// This is the recommended coding style to describe write-first synchronized byte-write enable functionality for Virtex-6,
// Spartan-6 and newer device families. This coding style is not supported for older device families. In that case, please refer
// to the corresponding 2-bit and 4-bit write enable templates for device families before Virtex-6 and Spartan-6.
//

 Avrum

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