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Visitor
Visitor
2,776 Views
Registered: ‎05-30-2017

adder2/adder3/adder4 synthesis using ISE

Hi

I have observed during synthesis of higher adders(width great than 5 or so) (adder5 and upwards) Xilinx uses carry chain but for adders with width 4 or less it just uses LUTs and no carry chains.

 

Has anyone else observed this? Any reasons

 

Is there a way to force it to use carry chain???

Thanks

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3 Replies
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Visitor
Visitor
2,722 Views
Registered: ‎05-30-2017

I would appreciate if someone could look at it and reply.Thanks

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Xilinx Employee
Xilinx Employee
2,614 Views
Registered: ‎05-14-2008

I don't have the exact reason but I think it is due to a balance of resource utilization and timing performance.

When the adder is small, using LUTs results in less utilization and the performance is good enough.

 

Why not just have XST to choose what resources to use?

Is there any special reason that you'd like to force using carry chain for small adders?

 

Thanks,

Vivian

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Moderator
Moderator
2,598 Views
Registered: ‎07-21-2014

@nomita,

 

I believe there must be an internal threshold defined in the XST to decide when to infer adders with carry chains, which can be tested with a small test case as already mentioned by you.

 

As already mentioned by Vivian, let the tool take decision on logic inference.

However, if you want to force the inference, please use use_carry_chain attribute on the signal declaration. This will push the logic into the carry chains.

 

Thanks,
Anusheel
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