We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


Showing results for 
Search instead for 
Did you mean: 

Welcome to the Synthesis Community Forum. This community should serve as a resource to ask and answer questions related to Vivado™ Synthesis, XST™, 3rd party synthesis tools, HDL coding practices and tips.

Xilinx Synthesis solutions are used for generations and many resources are available to help design and debug. Please follow these steps to most efficiently find your answer:

  • 1. Search this community for your question/issue
  • 2. Reference the sticky note topic for resources including documentation, known issues, debug guide, and frequently asked questions
  • 3. Post your question – leverage the vast community knowledge and the many Xilinx experts available on this board for help with your specific question

Most Recent Threads

Before you post, please read our Community Forums Guidelines or to get started see our Community Forum Help.


Top Kudoed Authors