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Visitor etti411g
Visitor
4,526 Views
Registered: ‎08-17-2011

editing rtl schematic

i'm trying to synthesis a structural vhdl code, and my question is, if there is any posibility to edit the rtl schematic. Also i want to save it and convert it into structural code? 

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Xilinx Employee
Xilinx Employee
4,523 Views
Registered: ‎05-14-2008

Re: editing rtl schematic

You cannot edit the RTL Schematic.

 

You can use Netgen to generate post-synthesis (gate-level) simulation model file. Not sure if this is the structural code you want. Refer to "Command Line tools User Guide" for information of Netgen.

 

Vivian

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Visitor etti411g
Visitor
4,520 Views
Registered: ‎08-17-2011

Re: editing rtl schematic

ok, thanks, but verilog source can be converted ratter in a schematic source type?

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Historian
Historian
4,512 Views
Registered: ‎02-25-2008

Re: editing rtl schematic


@etti411g wrote:

ok, thanks, but verilog source can be converted ratter in a schematic source type?


My parser blew up on this.

----------------------------Yes, I do this for a living.
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