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Newbie vtbvtb
Newbie
3,669 Views
Registered: ‎09-11-2012

how to change variable in case statement

Hello, 

I have a problem with logic of case statement in vhdl. I wonder if the variable that selects the case condition can be changed within the statement. To clarify: 

process(clk) 

variable aaa: std_logic_vector(2 downto 0):="000"; 

case  aaa  is 

    when  "000"  => 
      if () then 
        something 
      end if; 
      aaa := aaa+1; 

    when  "001" => 

        if() then
      something 

        elsif() then

        something

         else

         something

       end if;
      aaa := aaa+1; 

    when others => 
      -- sequential statements 


end   case ; 

end process; 

When I tried to synthesize a code with that algorithm, it displays an error. What is the problem here? Can't I change the variable within the case? Or the problem is about the if statements in the case? 

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2 Replies
Advisor eilert
Advisor
3,644 Views
Registered: ‎08-14-2007

Re: how to change variable in case statement

Hi,

you should have stated the error message.

 

According to your question, it is no problem to change the selecting variable. This is done all the time e.g. in FSMs where you change the state variable according to its actual value and some input conditions.

 

But I guess your error message is about the "+" operator.

aaa is a std logic vector and can not directly be added to an integer.

It depends on the libraries you are using what data types can be used with the "+" operator.

 

You should use numeric_std. Is this in your library usage lines above your entity declaration?

If not, add it.

 

Then the adder lines need to be changed like this:

 

aaa <= std_logic_vector(unsigned(aaa) + 1));

 

This nasty casting could be avoided if aaa would be declared as unsigned.

 

Another way would be to use a mathicng type for the 1.

 

aaa <= aaa + "001";

 

But this coding is quite inflexible, e.g. if you choose a different vector size for aaa.

Think about code reuse.

 

Have a nice synthesis

  Eilert

 

 

 

 

 

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Historian
Historian
3,608 Views
Registered: ‎02-25-2008

Re: how to change variable in case statement


 

But I guess your error message is about the "+" operator.

aaa is a std logic vector and can not directly be added to an integer.

It depends on the libraries you are using what data types can be used with the "+" operator.

 

You should use numeric_std. Is this in your library usage lines above your entity declaration?

If not, add it.

 

Then the adder lines need to be changed like this:

 

aaa <= std_logic_vector(unsigned(aaa) + 1));

 

This nasty casting could be avoided if aaa would be declared as unsigned.

 

Another way would be to use a mathicng type for the 1.

 

aaa <= aaa + "001";

 

But this coding is quite inflexible, e.g. if you choose a different vector size for aaa.

Think about code reuse.

 


Of course, the variable which drives the case statement need not be a std_logic_vector. Just make it a ranged natural and be done with it.

----------------------------Yes, I do this for a living.
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