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Explorer
Explorer
1,613 Views
Registered: ‎01-04-2013

how to synthesis demo zcu102_es2_base_trd?

Hello everyone

I'm trying to synthesis rdf0429-zcu102-es2-base-trd-2017-2-rev2 with vivado2017.2,but I encounter some error during synthesis

1.

TIM截图20180115100558.png

the IPs shown in the picture are generated from vivado hls

2.If I restart the synthesis process without any editor for some times ,sometimes it will generate bit stream successfully even!!

  Additional the bitstream generated can also used for linux

3.After generate bit stream successfully,I still find a synthesis error even !!

TIM截图20180115101327.png

4.When I open synthesised design or implemented design,after a long time,the process still stay at 17%

TIM截图20180115101644.png

Thanks for you replying

Best Wishes.

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11 Replies
Moderator
Moderator
1,528 Views
Registered: ‎09-15-2016

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @danpianji88

 

Can you try reset output products followed by generate output products with global mode selected by going to .bd file in the source hierarchy and right click?

Which OS you are using? If it is Windows then possibily an issue with path length (can't exceed 260 characters in Windows).

Can you try in latest Vivado version 2017.4 and let us know if you face any issue there.?

 

Regards

Rohit

Regards
Rohit
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Moderator
Moderator
1,502 Views
Registered: ‎09-15-2016

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @danpianji88,

 

Since these IPs came from HLS, did you see issues with C/RTL Cosimulation?

Also, in addition to the packaged output formats and RTL files (during HLS export), these directories should also contain project files for the Vivado Design Suite (.xpr). Opening the file project.xpr causes the design (Verilog or VHDL) to be opened in a Vivado project where the design may be analyzed for issues before migrating them to main project.

Regards,
Prathik
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Explorer
Explorer
1,494 Views
Registered: ‎01-04-2013

Re: how to synthesis demo zcu102_es2_base_trd?

TIM截图20180116121716.png

 

Hi @prathikm

I have tried to search the directory for the Vivado Design Suite (.xpr),but I doesn't find it.

Can tell me how to find it

If I find it ,I can regenerate the ip

Best Wishes

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Moderator
Moderator
1,486 Views
Registered: ‎09-15-2016

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @danpianji88,

 

I think you are seeing the exported zip file which does not have this. You should see the .xpr project with the verilog/vhdl source in the following HLS project path: <project_path>\solutionx\impl\verilog or \vhdl --> project.xpr.

 

So my question/idea was before you added your custom IP in main project did you check it standalone by synthesizing it? Did the code pass in HLS tool without any issues?

 

Regards,
Prathik
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Explorer
Explorer
1,481 Views
Registered: ‎01-04-2013

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @prathikm

I didn't find any path like "<project_path>\solutionx\impl\verilog or \vhdl --> project.xpr" in the demo,the demo rdf0429-zcu102-es2-base-trd-2017-2-rev2.zip was down in xilinx wiki,I just unzip it ,and open the .xpr which is existed in it.But I can find .cpp and .h files in the directory project.ipdefs/ip_0

Should I new a HLS project with the .cpp and .h files and repackage the ip to IP Catalog

 

Thanks for your replying

 

Best Wishes

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Moderator
Moderator
1,465 Views
Registered: ‎09-15-2016

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @danpianji88,

 

Not sure which .zip or design files you are referring to...

 

But my point was to check the custom IP standalone in new project by synthesizing it to see if the above error is present or not, then add it in main design. Because from the error message it is difficult to trace where the issue should be.

 

If code came from HLS as IP, we need to make sure it first passes in HLS tool as discussed above without any issues or critical errors and then export the RTL.

 

Also you mentioned a strange behavior of write bitstream run being completed successfully and still the synthesis error is seen. Go to design runs, right click on synthesis run > do reset run > synthesize again and check. Maybe the errors are coming from the previous runs which you were testing, else it is not possible to move forward if tool throws error in synthesis stage.

 

Regards,
Prathik
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Explorer
Explorer
1,453 Views
Registered: ‎01-04-2013

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @prathikm

I find that the synthesis error is different from each synthesis.

I just synthesis the demo in vivado2017.4(ubuntu-64bit in virtual machine,and the host system is win7-64bit),and the synthesis erro is like below

QQ拼音截图20180118084803.png

The errors doesn't come from HLS IPs but some simpler IPs,this time I have reset output products by right click the BD and reset the synthesis process .

Before that,I had synthesised the demo in vivado2017.2(ubuntu-64bit in virtual machine,and the host system is win7-64bit),and the bitstream can be generated successfully.

 

I'm trying to build the demo manually and hope that be helpfull.

 

Regards

danpianji88

 

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Moderator
Moderator
1,447 Views
Registered: ‎09-15-2016

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @danpianji88,

 

Thanks for the update.

Can you please attach the log files of your runs?

Is the design available directly from some Xilinx link that we can download and check? Else can you please attach some test-case/your custom IP project here for us to check the synthesis run?

 

Regards,
Prathik
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Explorer
Explorer
1,440 Views
Registered: ‎01-04-2013

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @prathikm

Thank for your replying

I have checked some of the log files of the HLS IPs which synthesis fails that is because the length is too long,and have short the name of IPs in block design.

 

The log files attached below shows that some of verilog file of the IPs can't be find,but I doen't find them in the demo,can you tell me how find them.

 

The demo is downloaded from the web site http://www.wiki.xilinx.com/Zynq+UltraScale+MPSoC+Base+TRD+2017.2,you can go to chapter 3.3 to down the ZCU102 rev 1.0 / ES2 silicon

 

Can you synthesis for me in vivado2017.4 for OS windows7_64bit?

Regards

danpianji88

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Moderator
Moderator
601 Views
Registered: ‎09-15-2016

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @danpianji88,

 

Thank you for sharing more information.

 

I downloaded the ZCU102 rev 1.0 / ES2 silicon zip including all source code and project files and tried running in Vivado.

 

- You are correct. By default from the .zip file, the windows path length error for .xci files is seen upon IP Upgrade. The workaround you can use is to change the source file destination path rather than shorten the name of each IP. For example, after .zip file extraction, you are having path something like C:\Users\abc\Desktop\rdf0429-zcu102-es2-base-trd-2017-2-rev2\rdf0429-zcu102-es2-base-trd-2017-2. Just create a new folder and add the folders after hierarchy of the above path. Like the folder hierarchy below. This will solve path problem for some IPs and they will be upgraded if required.

 

h1.PNG

 

- Do Tools> Report IP Status and check what messages you observe.

 

- Also FYI that you make sure to see section 6.2 for the current TRD requirements and limitations before moving forward from the above link that you shared.

 

I will update you on the observation from the design runs and logs.

 

Regards,
Prathik
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Moderator
Moderator
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Registered: ‎09-15-2016

Re: how to synthesis demo zcu102_es2_base_trd?

Hi @danpianji88,

 

Can you confirm the below requirement is met at your end as per 6.2 from Wiki link above?

 

issue.PNG

 

Are you seeing the below when you open the design? If yes, then we might have a reason for the errors.

 

issue2.PNG

 

Regards,
Prathik
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