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Explorer
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Registered: ‎02-04-2013

inferring BRAM with single clock cycle read latency

Hello everybody,

I would like to infer a BRAM with single clock cycle read latency - i would like the BRAM output to act as First Word Fall Through FIFO.

- First i tried to use the BRAM with asynchronous read (as suggested in UG901(page 110) : Asynchronous Read Coding Example) but synthesis reports "Unsupported RAM template" error. Does anybody have an idea why?

- Then i tried to use the synchronous BRAM and code the the design in two-stage process with BRAM address logic in combinatorial section, this should also result in single clock cycle read latency. It seems to work, but simulation displays some undefined (XX) read values from initialized BRAM. Please see the code and simulation below. Does anybody have an idea why is the data read from BRAM undefined (please see below X0XX)?

Is there some other way to code BRAM to act as First Word Fall Through FIFO on the output?

 

 

 

 

bram_addr_B <= to_integer(unsigned(bram_mac_addr(MEM_DEPTH downto 1)));

  bram_port_B : process(clk_mac_i)
  begin
    if rising_edge(clk_mac_i) then

      -- write
      if (bram_mac_wren = '1') then
        bram_h(bram_addr_B) <= bram_mac_wdata(15 downto 8);
        bram_l(bram_addr_B) <= bram_mac_wdata(07 downto 0);
      end if;

      -- read
      bram_mac_rdata(15 downto 8) <= bram_h(bram_addr_B);
      bram_mac_rdata(07 downto 0) <= bram_l(bram_addr_B);

    end if;
  end process;
-- this reports Unsupported RAM template --bram_mac_rdata(15 downto 8) <= bram_h(bram_addr_B); --bram_mac_rdata(07 downto 0) <= bram_l(bram_addr_B);

bram_to_fifo_COMBINATORIAL : process (fifo_state, dv_i, last_bram_mac_addr, bram_mac_addr)
  begin
    -- default states
    bram_mac_addr <= std_logic_vector(to_unsigned(2044,bram_mac_addr'length));

    case fifo_state is
      when transmitting =>
        if ( dv_i = '0') then
          bram_mac_addr <= std_logic_vector(unsigned(last_bram_mac_addr) + 1);
        else
          bram_mac_addr <= last_bram_mac_addr;
        end if;

      when others =>
    end case;
  end process;

-- BRAM initial values
signal bram_h : ram_type := ( x"a0", x"a1", x"a2", x"a3", x"a4", x"a5", x"a6", x"a7", x"a8", x"a9", ...
signal bram_l : ram_type := ( x"b0", x"b1", x"b2", x"b3", x"b4", x"b5", x"b6", x"b7", x"b8", x"b9", ...


 

sim.png
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