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Visitor
Visitor
541 Views
Registered: ‎03-19-2015

latches not including in the longest logical path?

Why latches are treat by Vivado and XST like wires (neutral elements) for counting the longest logical path? Is this related with delay/propagation time of latches which is smaller than LUT/CARRY delays?

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Re: latches not including in the longest logical path?

Latches have two kinds of timing arcs.

One is similar to the flipflop's setup/hold. In this case, latches are treated as endpoints.

For the other timing arc, latches act like combinational logic. This is due to the nature of latch -- when G is asserted Q=D, just like a wire.

-vivian

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Visitor
Visitor
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Registered: ‎03-19-2015

Re: latches not including in the longest logical path?


@viviany wrote:

This is due to the nature of latch -- when G is asserted Q=D, just like a wire.


But how about propagation time (delay) of latch? Is it significantly smaller than LUT delay and therefore can be treated as wire by Vivado for counting longest logical path purposes?

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Teacher
Teacher
410 Views
Registered: ‎07-09-2009

Re: latches not including in the longest logical path?

I think the quick answer is the tools don't cope well with latches,
99.999 % of all designs would be RTL with registers.
I'll be interested in your work, and how your coping ,
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Visitor
Visitor
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Registered: ‎03-19-2015

Re: latches not including in the longest logical path?


@drjohnsmith wrote:
I think the quick answer is the tools don't cope well with latches

So synthesis tools should not ignore latch in critical path/longest logical path?

Anyone from Xilinx employees could confirm or deny it?

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: latches not including in the longest logical path?

did not say anything about tools ignoring,
they are just not good with latches,

normaly the engineers work is to AVOID latches in designs,
this link from "the experts"
https://www.doulos.com/knowhow/fpga/latches/


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Visitor
Visitor
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Registered: ‎03-19-2015

Re: latches not including in the longest logical path?


@drjohnsmith wrote:
did not say anything about tools ignoring,
they are just not good with latches,

normaly the engineers work is to AVOID latches in designs,
this link from "the experts"
https://www.doulos.com/knowhow/fpga/latches/



So, if they were better, they should include latches in the critical path calculation? Or latches can/may not be included for some reason (which is the reason?)?

I know latches are generally bad thing causes several problems with timing, verification etc. and user should avoid it unless knows exactly what is doing. My question is different: why Vivado/XST do not count latches as elements in the longest logical path?

 

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Teacher
Teacher
330 Views
Registered: ‎07-09-2009

Re: latches not including in the longest logical path?

Can I ask why you want latches ?
The use of them, is very usual, so Im interested in the application and how your using it and the tools .
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor
Visitor
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Registered: ‎03-19-2015

Re: latches not including in the longest logical path?


@drjohnsmith wrote:
Can I ask why you want latches ?
The use of them, is very usual, so Im interested in the application and how your using it and the tools .

I have got a design with several latches and LUTs in the path, and this path is supposed by me to be the longest logical path in the project but it not, becasues latches are not included and I am wonder why are not included?

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Teacher
Teacher
299 Views
Registered: ‎07-09-2009

Re: latches not including in the longest logical path?

Sorry, I obviously did not explain well,
Im always after examples of new techniques,
so Im wondering what your doing with the Latches and LUTs ,
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Visitor
Visitor
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Registered: ‎03-19-2015

Re: latches not including in the longest logical path?

I just have some (not my own) project and I wonder why the synthesis tools do not take into account the latches when counting the longest logical path, that's it. So far I still do not know why...

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Teacher
Teacher
221 Views
Registered: ‎07-09-2009

Re: latches not including in the longest logical path?

In that case,
Are you certain of the validity of the code ?
Latches are normally caused by codding errors,
so unless its a lump of IP you have purchased, I'd strongly suggest first you do find out why the latches are made,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
190 Views
Registered: ‎05-14-2008

Re: latches not including in the longest logical path?

OK. Now I'm curious of what paths you're referring to.

Are you using ISE or Vivado?

Could you show us the "longest path" you're referring to in Schematic or Timing report?

Why do you think latches are treated as "wire"?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Visitor
Visitor
167 Views
Registered: ‎03-19-2015

Re: latches not including in the longest logical path?


@drjohnsmith wrote:
In that case,
Are you certain of the validity of the code ?
Latches are normally caused by codding errors,
so unless its a lump of IP you have purchased, I'd strongly suggest first you do find out why the latches are made,

My project is 100% ok and doing exactly what I want. The problem is NOT with the design containing latches, I have got problem with answer WHY synthesis tools (Vivado, XST) do NOT counted latches as element for logical path?

@viviany wrote:

OK. Now I'm curious of what paths you're referring to.

Are you using ISE or Vivado?

Could you show us the "longest path" you're referring to in Schematic or Timing report?

Why do you think latches are treated as "wire"?

-vivian


Here is some example to clarify the issue:

module top
#(
    parameter N = 5
)
(
    input  A,
    input  [N-1:0] G,
    output Q
);

    reg [N-1:0] A_LATCHED;
    wire DATA1, DATA2;
    
    always @* 
    begin
        if(G[0])
            A_LATCHED[0] <= ~A;
    end
        
    genvar i;
    generate
        for (i=0; i<N-1; i=i+1)
            always @* 
            begin
                if(G[i+1])
                    A_LATCHED[i+1] <= ~A_LATCHED[i];
            end
    endgenerate

    
    assign Q = A_LATCHED[N-1];

endmodule

LUT -> LATCH -> LUT -> LATCH -> LUT -> LATCH -> LUT -> LATCH -> LUT -> LATCH. Vivado and XST reports:

Vivado: | Logic Levels | 1 |

XST: Offset: 0.332ns (Levels of Logic = 1)

Latch in this case is treat like endpoint, why not like ordinary LUT?

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