cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
eng.amr2009
Explorer
Explorer
8,119 Views
Registered: ‎12-21-2009

maximum combinational path delay

Jump to solution

I have been working on a pure combinational design

to realize the design time performance i examined the timing analysis provided by the synthesis report but the problem is tht synthesis report timing analysis is just estimates and the real delay should be measured after place and route process

my question is how can i find the maximum combinational path delay for a PURE COMBINATIONAL DESIGN where the PAR report does not contain any timing analysis in case of pure combinational logic

i looked up the asynchronous delay report but it provides a decending oreder of net delays, IS the maximum combinational path delay is the maximum net delay provided in the table included in the asynchronous delay report ?!!!!!

and thanks in advance 

0 Kudos
1 Solution

Accepted Solutions
eng.amr2009
Explorer
Explorer
10,072 Views
Registered: ‎12-21-2009

i found the solution

 

in the static timing report we set the report unconstraied paths (which is default blank)  to 1 or higher so the tool can report the maximum combinational path delay after the place and route without clock constrains

View solution in original post

0 Kudos
3 Replies
evgenis1
Advisor
Advisor
8,100 Views
Registered: ‎12-03-2007

What exactly your pure combinational design do? Do you have all ports of the design connected to the FPGA pins?

 

 

 

OutputLogic 

Tags (1)
0 Kudos
eng.amr2009
Explorer
Explorer
8,077 Views
Registered: ‎12-21-2009

it's a simple 8bit ripple adder

the inputs and outputs of the design is already connected to the IOB as they are the entity ports 

 

i want to know if there is another way to measure maximum combinational path delay for unclocked design after place and route

instead of synthesis report which is just estimates !!!!

 

i had to infer registers at the inputs and outputs of the entity(make the design clocked) to force the tool to make advanced timing analysis provided by the static timing analysis report after place and route

 

0 Kudos
eng.amr2009
Explorer
Explorer
10,073 Views
Registered: ‎12-21-2009

i found the solution

 

in the static timing report we set the report unconstraied paths (which is default blank)  to 1 or higher so the tool can report the maximum combinational path delay after the place and route without clock constrains

View solution in original post

0 Kudos