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ecarajesh@gmail.com
Contributor
Contributor
9,040 Views
Registered: ‎08-07-2013

one of the entity in top level deisgn reamins as a blackbox with no binding

I had synthesized and created the bit file also for one ISE project (ADC_and_refrence) to collect the 16 bit ADC digital output and sending at the rate 20micro second per sample. And also, i have modeled the PID controller in xilinx system generator/Matlab simulink to generate HDL netlist into the folder "xilinx_PID_controller". To execute my closed loop, i want to integrate these two files into one top level design as shown below.RTL_view_of_TOP_level_design.PNG while doing top level design , i copied both folders(i.e.ADC_and_refrence and xilinx_PID_controller ) into the working folder in which i am designing the top design called PID_controllelr_TOP_module.Before adding the xilinx_PID_controller entity in the top module, i had changed its library by using the command: xlSwitchLibrary('xilinx_PID_controller', 'work', 'pid_clsd_lib') , so that library file names should not clash with each other.  After adding,i tried to synthesize the top module, i have got the following warnings:

 

Synthesis warnings:
HDLCompiler:89 - "D:\HIL\FINAL\ISE_DESIGN\xilinx_forum\xilinx_full_PID_controller\PID_controller_TOP_module.vhd" Line 60: <xilinx_pid_controller_cw> remains a black-box since it has no binding entity.
Xst:1581 - Constraint "TIG" is only supported in a XCF file outside the BEGIN MODEL/END section.
Xst:1581 - Constraint "TIG" is only supported in a XCF file outside the BEGIN MODEL/END section.
Xst:2677 - Node <Inst_ADC_and_reference/data_ready> of sequential type is unconnected in block <PID_controller_TOP_module>.(this  is only warning i know)

 

 Among the above warnings, i am thinking that first warning is more considerable for rectification to get the exact implementation. Becuase, even though iam able to generate the bit file for top module it is not giving results satisfactorily.

Any help will be grately appreciable. Thanks in advance,

Regards,

P.RAJESH 

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6 Replies
vuppala
Xilinx Employee
Xilinx Employee
9,026 Views
Registered: ‎04-16-2012

Hi ecarajesh@gmail.com

 

Check this answer record: http://www.xilinx.com/support/answers/39980.html

 

Thanks,

Vinay

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ecarajesh@gmail.com
Contributor
Contributor
9,015 Views
Registered: ‎08-07-2013

Dear Vinay,

I had read that post after i got this warning. But , it seems that it is not matching to our case.In my perception, the problem is not how to instantiate the black box but how to instantiate one xilinx generator HDL netlist as a sub component or entity in the top level design. Because, i already followed all the things suggested by that link,that you have tagged in your replay. In fact, i am googling for the right information from two days, but it went vain. Hence, i decided to post the message here, so that it will be helpful to remaining people also. Still, if you need any further information regarding to clear understanding my problem,kindly asked me. 

 Thanks

P.Rajesh

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vuppala
Xilinx Employee
Xilinx Employee
8,970 Views
Registered: ‎04-16-2012

Hello Rajesh,

 

Can you add the Xilinx_PID_controller directory in the search directories (-sd) option of synthesis settings.


Thanks,

Vinay

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ecarajesh@gmail.com
Contributor
Contributor
8,958 Views
Registered: ‎08-07-2013

Dear Vinay,

            Thanks for your replay, I added the all required source files for top module in the design window pane as shown below. 

 

design_pane.PNG

 

 I have saved the project in 'xilinx_full_PID_controller' folder in which i copied the 'ADC_Refrence' folder and 'xilinx_pid_controller' netlist folder first and then i added to the to level design in design pane using add source option.

But according to .prj file as shown below , it seems that only ADC_and_refrence.vhd and PID_controller_TOP_module.vhd files only compiled. 

prj_file_for_TOP_design.PNG

 

Please, kindly, advice some procedure to add that XST generated netlist file to top design.

 Thanks

P.Rajesh

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vuppala
Xilinx Employee
Xilinx Employee
8,947 Views
Registered: ‎04-16-2012

Hello Rajesh,

 

As I mentioned in my post, add the directory path in -sd option of synthesis and translate process.

See snapshot:

translate.PNG

Thanks,

Vinay

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ecarajesh@gmail.com
Contributor
Contributor
8,937 Views
Registered: ‎08-07-2013

Dear vinay,

               I added the dierectory path in -sd option, but, still, no improvment. Same number of warnings are sustained. I will send you the HDL netlist folder and Ise project file of top module through private message, can you just verify once such that how we can integrate that XSG file with another HDL file without that warning.

Thanks,

P.Rajesh 

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