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Prasandh92
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Registered: ‎02-19-2021

"[Synth 8-327] inferring latch for variable" warnings in vivado

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The below continuous assign statement causing latch inference,

assign cmd_din = cmd_wr_en?cmd_din_reg:cmd_din;

Like these many warnings as inferring latch,

How do I change this logic?

 

Regards

Prasanth S

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richardhead
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Registered: ‎08-01-2012

Latches are generally a bad thing as they cannot be timed during timing analysis, and you'll probably end up with issues in hardware

I suggest simply removing the latch, and simply connect it to the true state always. Remember, in AXI, if a valid signal is LOW, then the rest of the signals are meaningless and can be anything. There is no need to set an address to 0 when valid is low. Usually you just keep it at the old value (via a register)

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richardhead
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Registered: ‎08-01-2012

Are you sure it is this line and not a knock on from elsewhere? this construct is simply a mux.

Please post the whole code.

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Prasandh92
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Registered: ‎02-19-2021

Please find the warning messages and corresponding lines,

[Synth 8-327] inferring latch for variable 'cmd_din' ["C:/Users/psathyam/backend_design_working_v1_ref6/ddr4_0_ex/ddr4_0_ex.srcs/sources_1/new/ddr_buffer.v":186]

assign cmd_din = cmd_wr_en?cmd_din_reg:cmd_din;

[Synth 8-327] inferring latch for variable 'temp_awaddr' ["C:/Users/psathyam/backend_design_working_v1_ref6/ddr4_0_ex/ddr4_0_ex.srcs/sources_1/new/user_m_axi.v":267]

assign temp_awaddr = (axi_awvalid && axi_awready)?{2'b00,cmd_fifo_dout[27:0]}: temp_awaddr;

[Synth 8-327] inferring latch for variable 'axi_wdata' ["C:/Users/psathyam/backend_design_working_v1_ref6/ddr4_0_ex/ddr4_0_ex.srcs/sources_1/new/user_m_axi.v":203]

assign axi_wdata = (axi_wvalid_reg1 && axi_wready)? write_fifo_dout:axi_wdata;

[Synth 8-327] inferring latch for variable 'temp_araddr' ["C:/Users/psathyam/backend_design_working_v1_ref6/ddr4_0_ex/ddr4_0_ex.srcs/sources_1/new/user_m_axi.v":326]

assign temp_araddr = (axi_arvalid && axi_arready)? {2'b00,cmd_fifo_dout[27:0]}: temp_araddr;

attaching the module below

Thanks in advance

Prasanth S

 

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richardhead
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Registered: ‎08-01-2012

Actually, just re-reading properly, of course this is a latch.

You are asking it to hold its value when cmd_wr_en = 0.  This is the definition of a latch. 

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Prasandh92
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Registered: ‎02-19-2021

Yes you are right.

My question is will it affect during synthesis or implementation in hardware?

If it is so, how do I re-write this logic?

Thanks in advance

Prasanth S

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richardhead
Scholar
Scholar
212 Views
Registered: ‎08-01-2012

Latches are generally a bad thing as they cannot be timed during timing analysis, and you'll probably end up with issues in hardware

I suggest simply removing the latch, and simply connect it to the true state always. Remember, in AXI, if a valid signal is LOW, then the rest of the signals are meaningless and can be anything. There is no need to set an address to 0 when valid is low. Usually you just keep it at the old value (via a register)

View solution in original post

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