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intern1
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4,921 Views
Registered: ‎01-22-2019

"[Synth 8-448] named port connection 'clk' does not exist" Error received during synthesis when using imported IP module.

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Hey All,

**I will attach a picture of my IP diagram, Error message readout and "instance" where the error is occuring**

I am recieving an error when attempting to synthesize my block project. I have recently updated an IP called "BPSK_modulator" and ran the IP upgrade in Vivado, however when I attempt to synthesize the design I recieve an error messgage that points me to an automatically generated Vivado file. 

The message is saying that the port connection 'clk' doesn't exist, I don't understand what this means? My port is connected and I can see that the modules "instance" was called with the port connection. 

I have read through https://forums.xilinx.com/t5/Design-Entry/Synthesis-error/td-p/703658 however it seems that the solution for their problem was to not disable a library file. I have not explicitly disabled any such files, so I am a little confused as to why this error is thrown. 

My previous design with my old "BPSK_modulator" IP synthesized fine. Any help is greatly appreciated!

Thank you! 

bpsk_modulator_error_messages.PNG
BPSK_Xilinx_forum_post.PNG
Error_BPSK_Modulator.PNG
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1 Solution

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anusheel
Moderator
Moderator
4,899 Views
Registered: ‎07-21-2014

@intern1 

I believe there is an IP found by the tool which looks duplicate of this IP and I guess tool is taking consideration of that IP while synthesizing the IP.

Can you try to eliminate the warning and make sure updated IP in the repository and in the project is same?

Thanks
Anusheel 

View solution in original post

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anusheel
Moderator
Moderator
4,900 Views
Registered: ‎07-21-2014

@intern1 

I believe there is an IP found by the tool which looks duplicate of this IP and I guess tool is taking consideration of that IP while synthesizing the IP.

Can you try to eliminate the warning and make sure updated IP in the repository and in the project is same?

Thanks
Anusheel 

View solution in original post