07-20-2021 11:26 PM - edited 07-21-2021 12:50 AM
I'm doing RTL code for some functions, and then I encountered a problem.
Does anybody know if it will happen timing violation if I shift 500 bits to a register in one clock .
If yes, what is the limit of bits that I can shift in one clock.
07-20-2021 11:52 PM
I'm sorry, this makes no sense,
what language are you designing in , HLS , RTL, C ?
May be my mantra might be of help here
"remember you describing hardware you want the tools to make"
if you can not design ( at least in outline ) the logic circuits, then the tools are unlikely to have much luck
07-21-2021 09:15 AM
have you edited your question,
it clearly has verilog in it , which is did not.
that now makes my question seem stupid.
07-21-2021 09:21 AM
so what you are looking for is 500, 2 to 1 multiplexers,
not exactly hard
07-21-2021 09:27 AM
A shift register doesn't shift one by one until the number you want. So it's the same to shift one position than one thousand.
Said that, be aware of:
- Operations on large registers mean many operations in parallel, and that can produce congestion and timing failing (but not the shift amount itself)
- Functions using large registers create busses that also are a magnet for congestions that reveal as placement errors or timing failures.
07-21-2021 07:37 PM
First, thank you all for your replies. I benefited a lot !
The last question. if I code like this below , it wouldn't produce congestion or timing violation. right?
07-22-2021 02:37 AM
its impossibel to say
If youw ere in a small artix 7, or a CPLD, you might have problems
in an ultra scale you are unlikely to , unless the design is already full
Its like saying, is this plate of food enough ?
depends on the recipiant !
BTW: Your in Verilog, not my favorit language,
but may be some one else can jump in , that if (!rstn) || init ) begin
07-22-2021 08:08 AM
I just had doubts, so thought I'd ask
why do you need asynchronous reset,
you have a constant clock ?
An asynchronous reset has potential to just adds routing / congestion which I know you are concerned about
why do you need a synchronous reset ?
FPGA s power up to a known / defined state .
07-23-2021 02:21 AM
Why do you think that using asynchronous reset saves the resources / cost ?
07-24-2021 04:26 AM
Thinking is not knowing,
and ASICs are not FPGAs
And this is a FPGA companies site,
07-24-2021 09:50 AM
Xilinx have recommended avoiding using a reset whenever possible for a long time and Im pretty sure it still holds for the more modern families: https://www.xilinx.com/support/documentation/white_papers/wp272.pdf
In Xilinx FPGAs particularly, you tend to run out of routing resources before logic resources, and that unneeded reset is just using the routing.