signals name getting change after synthesis on vivado 2015.4

[ramesh.d2015]

Hi All,

I have three modules as mentioned below,

top_module (it has 4 AXI DMA master engines), arbiter and AXI DMA slave module(MIG user interface). The top_module talking to the arbiter and arbiter talking to the MIG UI. I wanted to add the debug core for output AXI signals of top_module and output AXI signals of the arbiter. After synthesis I opened the schematic and marked required signals for debug from arbiter to MIG UI, while trying to add the top_module to arbiter signals I couldn't find the signals like AWVALID,AWREADY,WVALID,WREADY etc.

But signals are there with different names like mem_q[39:0],D[19:0] etc. The above mentioned AXI signals are may be declared as wire in the DMA engines not reg. 

How to add these signals into ILA core. Please help me.

Thanks,

[arpansur · Accepted solution]

Hi @ramesh.d2015,

Can you try putting mark_debug in HDL?

Then use setup debug to add the debug signals.

[ramesh.d2015]

Hi Arpan,

sure, I'll try with mark_debug in the HDL. I didn't try this so far.

Thank you very much, I'll get back to you asap.

-ramesh 

[steve_av]

Another thing to look at is the synthesis settings "flatten_hierarchy" , it may be set to something other than NONE.

[ramesh.d2015]

Hi Arpan,

Its works perfectly!!!, though the signals are declared as wire in the design I could able to add those into debug core by mark_debug. Thank you very much.

-ramesh